diff mbox series

[U-Boot,U-boot,v3,13/14] ARM: dts: at91: sam9x60ek: Enable qspi node

Message ID 20190927130818.478-14-tudor.ambarus@microchip.com
State Accepted
Commit 228f9e0244960c9823ebcecf3bb0e4e06dc0420f
Delegated to: Eugen Hristev
Headers show
Series Add support for sam9x60ek | expand

Commit Message

Tudor Ambarus Sept. 27, 2019, 1:09 p.m. UTC 
From: Tudor Ambarus <tudor.ambarus@microchip.com>

The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory.

Enable the qspi node together with the SST26VF064B qspi nor flash
memory. Booting from the QSPI NOR flash is now possible.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
 arch/arm/dts/sam9x60.dtsi          | 29 +++++++++++++++++++++++++++++
 arch/arm/dts/sam9x60ek-u-boot.dtsi | 28 ++++++++++++++++++++++++++++
 arch/arm/dts/sam9x60ek.dts         | 31 +++++++++++++++++++++++++++++++
 3 files changed, 88 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index a66d0a278a87..9c16ba1e6a87 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -22,6 +22,7 @@ 
 		serial0 = &dbgu;
 		gpio0 = &pioA;
 		gpio1 = &pioB;
+		spi0 = &qspi;
 	};
 
 	clocks {
@@ -60,6 +61,17 @@ 
 			#size-cells = <1>;
 			ranges;
 
+			qspi: spi@f0014000 {
+				compatible = "microchip,sam9x60-qspi";
+				reg = <0xf0014000 0x100>, <0x70000000 0x10000000>;
+				reg-names = "qspi_base", "qspi_mmap";
+				clocks =  <&qspi_clk>, <&qspick>;
+				clock-names = "pclk", "qspick";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
 			macb0: ethernet@f802c000 {
 				compatible = "cdns,sam9x60-macb", "cdns,macb";
 				reg = <0xf802c000 0x100>;
@@ -172,6 +184,18 @@ 
 					atmel,clk-divisors = <1 2 4 6>;
 				};
 
+				system: systemck {
+					compatible = "atmel,at91rm9200-clk-system";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					qspick: qspick {
+						#clock-cells = <0>;
+						reg = <19>;
+						clocks = <&mck>;
+					};
+				};
+
 				periph: periphck {
 					compatible = "microchip,sam9x60-clk-peripheral";
 					#address-cells = <1>;
@@ -202,6 +226,11 @@ 
 						#clock-cells = <0>;
 						reg = <24>;
 					};
+
+					qspi_clk: qspi_clk {
+						#clock-cells = <0>;
+						reg = <35>;
+					};
 				};
 
 				generic: gck {
diff --git a/arch/arm/dts/sam9x60ek-u-boot.dtsi b/arch/arm/dts/sam9x60ek-u-boot.dtsi
index 68e220926e5e..93cf1262f6fc 100644
--- a/arch/arm/dts/sam9x60ek-u-boot.dtsi
+++ b/arch/arm/dts/sam9x60ek-u-boot.dtsi
@@ -31,6 +31,10 @@ 
 	u-boot,dm-pre-reloc;
 };
 
+&qspi {
+	u-boot,dm-pre-reloc;
+};
+
 &pinctrl_dbgu {
 	u-boot,dm-pre-reloc;
 };
@@ -39,10 +43,18 @@ 
 	u-boot,dm-pre-reloc;
 };
 
+&pinctrl_qspi {
+	u-boot,dm-pre-reloc;
+};
+
 &pioA {
 	u-boot,dm-pre-reloc;
 };
 
+&pioB {
+	u-boot,dm-pre-reloc;
+};
+
 &pmc {
 	u-boot,dm-pre-reloc;
 };
@@ -59,6 +71,14 @@ 
 	u-boot,dm-pre-reloc;
 };
 
+&system {
+	u-boot,dm-pre-reloc;
+};
+
+&qspick {
+	u-boot,dm-pre-reloc;
+};
+
 &periph {
 	u-boot,dm-pre-reloc;
 };
@@ -67,6 +87,10 @@ 
 	u-boot,dm-pre-reloc;
 };
 
+&pioB_clk {
+	u-boot,dm-pre-reloc;
+};
+
 &sdhci0_clk {
 	u-boot,dm-pre-reloc;
 };
@@ -75,6 +99,10 @@ 
 	u-boot,dm-pre-reloc;
 };
 
+&qspi_clk {
+	u-boot,dm-pre-reloc;
+};
+
 &generic {
 	u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index 6fe9f19f0bc7..63904272f08f 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -16,6 +16,37 @@ 
 	chosen {
 		stdout-path = &dbgu;
 	};
+
+	ahb {
+		apb {
+			qspi: spi@f0014000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_qspi>;
+				status = "okay";
+
+				nor_flash: sst26vf064@0 {
+					compatible = "spi-flash";
+					reg = <0>;
+					spi-max-frequency = <80000000>;
+					spi-rx-bus-width = <4>;
+					spi-tx-bus-width = <4>;
+				};
+			};
+
+			pinctrl {
+					pinctrl_qspi: qspi {
+						atmel,pins =
+							<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE
+							 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE
+							 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+							 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+							 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
+							 AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+					};
+
+			};
+		};
+	};
 };
 
 &macb0 {