From patchwork Mon Sep 23 08:59:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 1165928 X-Patchwork-Delegate: eugen.hristev@microchip.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=microchip.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=microchiptechnology.onmicrosoft.com header.i=@microchiptechnology.onmicrosoft.com header.b="kUS23sad"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46cJFS5mX6z9sP6 for ; Mon, 23 Sep 2019 19:00:44 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 5E52FC21D8A; Mon, 23 Sep 2019 08:59:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 39812C21D56; Mon, 23 Sep 2019 08:59:37 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2ED7AC21DB5; Mon, 23 Sep 2019 08:59:17 +0000 (UTC) Received: from esa3.microchip.iphmx.com (esa3.microchip.iphmx.com [68.232.153.233]) by lists.denx.de (Postfix) with ESMTPS id 4C2E6C21E0F for ; Mon, 23 Sep 2019 08:59:11 +0000 (UTC) Received-SPF: Pass (esa3.microchip.iphmx.com: domain of Tudor.Ambarus@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa3.microchip.iphmx.com; envelope-from="Tudor.Ambarus@microchip.com"; x-sender="Tudor.Ambarus@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com a:mx1.microchip.iphmx.com a:mx2.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa3.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa3.microchip.iphmx.com; envelope-from="Tudor.Ambarus@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa3.microchip.iphmx.com; spf=Pass smtp.mailfrom=Tudor.Ambarus@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dkim=pass (signature verified) header.i=@microchiptechnology.onmicrosoft.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: bCU9VeNoxCiHf/Pg1soCfHzUOXigwcc5FhCGN7A56fiN746wz5ylUHG5rhhzFIkuBgYUao6R6y 90Ums+rT+YOD/2F7t64z6nzzZjcMBvFQbpVejqSm80gcB+3KvKR9plH33n57r34LAAg4T6K368 H9IG42BAv9qTkSmvHphYqPkoXDeytUfvYF+NfTtWZhl+uWW0oHEjSmTN4RslOodpFzKzXHNfjd HBIullQObDPEGp0/WLW6OuioNGa5wZOmgXJhRbDVmMttqXYPNGjryyhOYJrnKjYK3/C0V9g/Pk /fM= X-IronPort-AV: E=Sophos;i="5.64,539,1559545200"; d="scan'208";a="50112758" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 23 Sep 2019 01:59:10 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Mon, 23 Sep 2019 01:59:09 -0700 Received: from NAM02-BL2-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.87.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Mon, 23 Sep 2019 01:59:09 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z7x8mJMcP9jcAQ3qib9PtfMK32w7LXtz/irmMcGHSDe8sJSB+mCZa4pRLywIKEgSEcq9+JS7UXLgMIO/8UNv+k0KtYuPZBqrpYnd98vja1v2U9cai6ozjnQJS81sVE1e226wsJGG1xxO0ccXkjUAtmzWOFskXEV+3lBTOsSgBA0efup4LYi5uUeW7aUJ/FOn8PEsr8WF77Oaret6u7sxs4fhsL9pqEVM83fGFhv45zwgd+rUs0HUZF2eH45nl7jbEsN5X/mWrk05WRVIPHUSW4y0NL98itjyYXm7ZIZt7x2ykOGfnu50/esordpjXpDNDehBKXh7CkZLY+tE2/C/mA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BhbS8MYjajybf44M1Zb5lz+JavUcp2khda1Y0nU1sJ0=; b=bGEh8Zqqv53MccPIoyTFvdJ8QM7l7OO65CYnf2HhCELMBbXwtneT/mUDgJvjDlANk6OxFKHGP8kQhj1G2D89ovZ/j6NGao4ssuMZzLiDdsUXyIL0c6ZeXJuhjlp8YwLytYdTG3RO1rW+gs9Xtfo2ODXMcu9dUB6tz2vpgKlM9IROyaBQq/VvU/srLEXmjyter487LNX/nVd6IReknbE3mZHiDpa1eHHOO9bJzO5f8XDX60Wk/tIiIQE/8mpUE6d1uM4A7xEaTlV7m5PFzcz9IUugQ/sNM1/Olzvma/zm946+C60m62cWJBbt+jJOepJhM9DxeDob5RvsEIicXbfnOA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=microchip.com; dmarc=pass action=none header.from=microchip.com; dkim=pass header.d=microchip.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector2-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BhbS8MYjajybf44M1Zb5lz+JavUcp2khda1Y0nU1sJ0=; b=kUS23sadCkWFF80LtQG/ByKDSgrrMNmvTRrQrK9nGFbssh1iFwzRawbF6gwlwbT6xRh5yeeolRfO6bgAyYdZmPkSzDb2JCcsscDsG9dn7L4XRdb3v+Fn4f2OA+NEr3bJyEHK27J4cJEoBsFpnyTCCHb/8L/T1Y9T675bYP8EyfM= Received: from MN2PR11MB4448.namprd11.prod.outlook.com (52.135.39.157) by MN2PR11MB4317.namprd11.prod.outlook.com (52.135.36.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2284.26; Mon, 23 Sep 2019 08:59:07 +0000 Received: from MN2PR11MB4448.namprd11.prod.outlook.com ([fe80::c951:b15a:e4b3:30f7]) by MN2PR11MB4448.namprd11.prod.outlook.com ([fe80::c951:b15a:e4b3:30f7%7]) with mapi id 15.20.2284.023; Mon, 23 Sep 2019 08:59:07 +0000 From: To: , , Thread-Topic: [PATCH v2 07/12] ARM: at91: Add SFR definitions Thread-Index: AQHVce0ovt1Sp/fork+NBOogFJnZ5Q== Date: Mon, 23 Sep 2019 08:59:07 +0000 Message-ID: <20190923085829.25171-8-tudor.ambarus@microchip.com> References: <20190923085829.25171-1-tudor.ambarus@microchip.com> In-Reply-To: <20190923085829.25171-1-tudor.ambarus@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR09CA0062.eurprd09.prod.outlook.com (2603:10a6:802:28::30) To MN2PR11MB4448.namprd11.prod.outlook.com (2603:10b6:208:193::29) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.9.5 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 72afce05-4674-4dd1-d0a0-08d740044a98 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600167)(711020)(4605104)(1401327)(2017052603328)(7193020); SRVR:MN2PR11MB4317; x-ms-traffictypediagnostic: MN2PR11MB4317: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:2276; x-forefront-prvs: 0169092318 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(346002)(39860400002)(376002)(366004)(136003)(396003)(199004)(189003)(50226002)(110136005)(52116002)(99286004)(186003)(1076003)(6506007)(305945005)(7736002)(86362001)(66946007)(66476007)(66556008)(478600001)(2501003)(386003)(66446008)(76176011)(107886003)(4326008)(64756008)(2201001)(6436002)(446003)(2616005)(6486002)(71190400001)(71200400001)(54906003)(6512007)(5660300002)(11346002)(6116002)(3846002)(25786009)(14454004)(256004)(476003)(36756003)(81156014)(8676002)(7416002)(2906002)(486006)(8936002)(81166006)(66066001)(102836004)(26005)(316002); DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR11MB4317; H:MN2PR11MB4448.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: aukYDh7QW/XJ82xe6PdTd2Dtaup+mApwKwxqYxBLg+aGbfFJR6lk1Zds9UCUDphX47mz3G44jst5UHIRs3kR7QZU+6Gd788NFaa0p1LWm5XpNOYmVhtFsRW7uX+OoixiJhskLkT7/5GAoDjrJTX3RycoZI2KQL54JxobJ8E4yTwgBJI+dJ7xdkwAVewqIXH2Tkc4QrUj4KbBM81O0Dh6lMvz3LdQvn/eRJFfC9OheqDOxXwqnc7ip727eO4Pon73S5XXIdQd4P+7zaO6MZTZlr04Qz3fUTjDXGMjonERPMFRrHLYvoVTVsN8KkfodjFpEsUGPqiTDtBOH0dO03rJWy2SCRJrVkbCeNxmjt5P7BIAzX1xR1V2G012xq5pGDXVHtqyg/qKaBwqYB29JgQDx/dNTa1AHCP4j3tDcr/trnE= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 72afce05-4674-4dd1-d0a0-08d740044a98 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Sep 2019 08:59:07.6077 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: xyNjuwVK5Ygj9TmxMgN57TKif7MYPht2R6pSS9+oGP3wEvRSjsmUZvt7VfjWwhSG1MrFVPbXNnbwa05KbjxZNLmyjLQsAvbTfG1TAlyQ06k= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4317 Cc: Nicolas.Ferre@microchip.com, Sandeep.Sheriker@microchip.com, sr@denx.de, Claudiu.Beznea@microchip.com, marek.vasut+renesas@gmail.com Subject: [U-Boot] [PATCH v2 07/12] ARM: at91: Add SFR definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tudor Ambarus sama5's SFR has at offset 0x04 the DDR Configuration Register, while sam9x60's SFR contains the EBI Chip Select Register. Add a union to reconcile both boards. Signed-off-by: Tudor Ambarus --- arch/arm/mach-at91/include/mach/at91_sfr.h | 48 ++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/include/mach/at91_sfr.h b/arch/arm/mach-at91/include/mach/at91_sfr.h index dc259055cff6..0300c336dd81 100644 --- a/arch/arm/mach-at91/include/mach/at91_sfr.h +++ b/arch/arm/mach-at91/include/mach/at91_sfr.h @@ -11,7 +11,10 @@ struct atmel_sfr { u32 reserved1; /* 0x00 */ - u32 ddrcfg; /* 0x04: DDR Configuration Register */ + union { + u32 ddrcfg; /* 0x04: DDR Configuration Register */ + u32 ebicsa; /* 0x04: EBI Chip Select Register */ + }; u32 reserved2; /* 0x08 */ u32 reserved3; /* 0x0c */ u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */ @@ -28,7 +31,16 @@ struct atmel_sfr { }; /* Register Mapping*/ +#define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */ +#define AT91_SFR_CCFG_EBICSA 0x04 /* EBI Chip Select Register */ +/* 0x08 ~ 0x0c: Reserved */ +#define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */ +#define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */ #define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */ +#define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */ +#define AT91_SFR_LS 0x7c /* Light Sleep Register */ +#define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */ +#define AT91_SFR_WPMR 0xe4 /* Write Protection Mode Register */ /* Bit field in DDRCFG */ #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 @@ -58,9 +70,39 @@ struct atmel_sfr { #define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12) #define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12) -#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) - /* Bit field in AICREDIR */ #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001 +/* Bit field in DDRCFG */ +#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 +#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 + +#define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs)) +#define AT91_SFR_CCFG_EBI_DBPUC BIT(8) +#define AT91_SFR_CCFG_EBI_DBPDC BIT(9) +#define AT91_SFR_CCFG_EBI_DRIVE_SAM9X60 BIT(16) +#define AT91_SFR_CCFG_EBI_DRIVE BIT(17) +#define AT91_SFR_CCFG_DQIEN_F BIT(20) +#define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24) +#define AT91_SFR_CCFG_DDR_MP_EN BIT(25) + +#define AT91_SFR_OHCIICR_RES(x) BIT(x) +#define AT91_SFR_OHCIICR_ARIE BIT(4) +#define AT91_SFR_OHCIICR_APPSTART BIT(5) +#define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x)) +#define AT91_SFR_OHCIICR_UDPPUDIS BIT(23) +#define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8) + +#define AT91_SFR_OHCIISR_RIS(x) BIT(x) + +#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) + +#define AT91_SFR_UTMISWAP_PORT(x) BIT(x) + +#define AT91_SFR_LS_VALUE(x) BIT(x) +#define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16) + +#define AT91_SFR_WPMR_WPEN BIT(0) +#define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8) + #endif