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H:MN2PR11MB4448.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: dUczPdIDLQZf1whQyDGcnWCqXucxLRlmFCSGyP4hkcH5oHHNvHTUhgs00fGD2hIPWSNONYZtzn2FONOFk9DlSIsXrANA3CeVnIm5VSGHh9s41MYWdtFDFMMRDfr7HUNN/+haSEMtl1n/SiBt7RkA38XyEmXUaKi3EzIhraCw+Hdz1Nnb85170zQTjE9bQAb4gKrlc0fWoLko3wFNSdXCl7afZSnEYm0rkXIxSIQMzOCNxqq0s38/d9PThNh+iS+tByfgCXuF7TF4oFdeyC/gqmN5Vq6iEbPYvc29FKmqOSWjichpkaIwRxZuP7HX2BRuTaILnZ8eM2i70Ry3gzu6pn0qwv/RqkEgXbJ6FD9OzzJj3GNF2Sn1sJp/KEboQXtmN6w81vHK1vFmxS1PlvRSpSaiEshlRPG/v6IJLGb73MM= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 8a5ab8f6-5700-40b4-da7d-08d73dcaf24e X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Sep 2019 13:03:35.5995 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 8gvbwg+lX1vaKbH1VZ0XHj0sTCuHp4vmiakviu3MuaAx5SPJx2EhigXxvmXfNb8/66knJ/0xjFAa4mlqtquOP/QKJJcig2cdDhn/Rxodmqc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB4221 Cc: Nicolas.Ferre@microchip.com, Sandeep.Sheriker@microchip.com, sr@denx.de, Claudiu.Beznea@microchip.com, marek.vasut+renesas@gmail.com Subject: [U-Boot] [PATCH 07/12] ARM: at91: Add SFR definitions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Tudor Ambarus sama5's SFR has at offset 0x04 the DDR Configuration Register, while sam9x60's SFR contains the EBI Chip Select Register. Add a union to reconcile both boards. Signed-off-by: Tudor Ambarus --- arch/arm/mach-at91/include/mach/at91_sfr.h | 48 ++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-at91/include/mach/at91_sfr.h b/arch/arm/mach-at91/include/mach/at91_sfr.h index dc259055cff6..0300c336dd81 100644 --- a/arch/arm/mach-at91/include/mach/at91_sfr.h +++ b/arch/arm/mach-at91/include/mach/at91_sfr.h @@ -11,7 +11,10 @@ struct atmel_sfr { u32 reserved1; /* 0x00 */ - u32 ddrcfg; /* 0x04: DDR Configuration Register */ + union { + u32 ddrcfg; /* 0x04: DDR Configuration Register */ + u32 ebicsa; /* 0x04: EBI Chip Select Register */ + }; u32 reserved2; /* 0x08 */ u32 reserved3; /* 0x0c */ u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */ @@ -28,7 +31,16 @@ struct atmel_sfr { }; /* Register Mapping*/ +#define AT91_SFR_DDRCFG 0x04 /* DDR Configuration Register */ +#define AT91_SFR_CCFG_EBICSA 0x04 /* EBI Chip Select Register */ +/* 0x08 ~ 0x0c: Reserved */ +#define AT91_SFR_OHCIICR 0x10 /* OHCI INT Configuration Register */ +#define AT91_SFR_OHCIISR 0x14 /* OHCI INT Status Register */ #define AT91_SFR_UTMICKTRIM 0x30 /* UTMI Clock Trimming Register */ +#define AT91_SFR_UTMISWAP 0x3c /* UTMI DP/DM Pin Swapping Register */ +#define AT91_SFR_LS 0x7c /* Light Sleep Register */ +#define AT91_SFR_I2SCLKSEL 0x90 /* I2SC Register */ +#define AT91_SFR_WPMR 0xe4 /* Write Protection Mode Register */ /* Bit field in DDRCFG */ #define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 @@ -58,9 +70,39 @@ struct atmel_sfr { #define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12) #define AT91_SFR_EBICFG_SCH1_ON (0x1 << 12) -#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) - /* Bit field in AICREDIR */ #define ATMEL_SFR_AICREDIR_NSAIC 0x00000001 +/* Bit field in DDRCFG */ +#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000 +#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000 + +#define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs)) +#define AT91_SFR_CCFG_EBI_DBPUC BIT(8) +#define AT91_SFR_CCFG_EBI_DBPDC BIT(9) +#define AT91_SFR_CCFG_EBI_DRIVE_SAM9X60 BIT(16) +#define AT91_SFR_CCFG_EBI_DRIVE BIT(17) +#define AT91_SFR_CCFG_DQIEN_F BIT(20) +#define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24) +#define AT91_SFR_CCFG_DDR_MP_EN BIT(25) + +#define AT91_SFR_OHCIICR_RES(x) BIT(x) +#define AT91_SFR_OHCIICR_ARIE BIT(4) +#define AT91_SFR_OHCIICR_APPSTART BIT(5) +#define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x)) +#define AT91_SFR_OHCIICR_UDPPUDIS BIT(23) +#define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8) + +#define AT91_SFR_OHCIISR_RIS(x) BIT(x) + +#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0) + +#define AT91_SFR_UTMISWAP_PORT(x) BIT(x) + +#define AT91_SFR_LS_VALUE(x) BIT(x) +#define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16) + +#define AT91_SFR_WPMR_WPEN BIT(0) +#define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8) + #endif