diff mbox series

[U-Boot,3/4] arm: mxs: be more careful when enabling gpmi_clk

Message ID 20190912091656.14301-4-rasmus.villemoes@prevas.dk
State Accepted
Commit abaf5c98047338c8d8774ff0a5cbc9efffda92f0
Delegated to: Stefano Babic
Headers show
Series arm: mxs: mxs_set_gpmiclk | expand

Commit Message

Rasmus Villemoes Sept. 12, 2019, 9:17 a.m. UTC 
The data sheet says that the DIV field cannot change while the CLKGATE
bit is set or modified. So do it a little more carefully, by first
clearing the bit, waiting for that to appear, then setting the DIV
field.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
---
 arch/arm/cpu/arm926ejs/mxs/mxs.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 585c53baf6..183aa40b6d 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -103,8 +103,11 @@  int arch_cpu_init(void)
 		&clkctrl_regs->hw_clkctrl_clkseq_set);
 
 	/* Set GPMI clock to ref_xtal / 1 */
+	clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE);
+	while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE)
+		;
 	clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
-		CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
+		CLKCTRL_GPMI_DIV_MASK, 1);
 
 	udelay(1000);