From patchwork Thu Aug 22 10:26:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1151464 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46Dgm06nMLz9s3Z for ; Thu, 22 Aug 2019 20:30:40 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 6BF8DC22057; Thu, 22 Aug 2019 10:28:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D110AC2208B; Thu, 22 Aug 2019 10:27:41 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6CC17C22075; Thu, 22 Aug 2019 10:27:31 +0000 (UTC) Received: from mxwww.masterlogin.de (mxwww.masterlogin.de [95.129.51.220]) by lists.denx.de (Postfix) with ESMTPS id 021CDC2205E for ; Thu, 22 Aug 2019 10:27:29 +0000 (UTC) Received: from mxout2.routing.net (unknown [192.168.10.82]) by new.mxwww.masterlogin.de (Postfix) with ESMTPS id 441C496D42; Thu, 22 Aug 2019 10:27:28 +0000 (UTC) Received: from mxbox3.masterlogin.de (unknown [192.168.10.253]) by mxout2.routing.net (Postfix) with ESMTP id AC6C2648E5; Thu, 22 Aug 2019 10:27:28 +0000 (UTC) Received: from localhost.localdomain (fttx-pool-217.61.154.89.bambit.de [217.61.154.89]) by mxbox3.masterlogin.de (Postfix) with ESMTPSA id 0C8AA36067D; Thu, 22 Aug 2019 12:27:28 +0200 (CEST) From: Frank Wunderlich To: u-boot@lists.denx.de Date: Thu, 22 Aug 2019 12:26:54 +0200 Message-Id: <20190822102656.4993-7-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190822102656.4993-1-frank-w@public-files.de> References: <20190822102656.4993-1-frank-w@public-files.de> Cc: Ryder Lee , GSS_MTK_Uboot_upstream Subject: [U-Boot] [PATCH v4 6/8] dt-bindings: phy: add a document for MediaTek tphy X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This adds a document for tphy which supports physical layer functionality for a number of controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- changes since v3: none changes since v2: dt-bindings added with v3 --- doc/device-tree-bindings/phy/phy-mtk-tphy.txt | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 doc/device-tree-bindings/phy/phy-mtk-tphy.txt diff --git a/doc/device-tree-bindings/phy/phy-mtk-tphy.txt b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt new file mode 100644 index 0000000000..037c5a4be5 --- /dev/null +++ b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt @@ -0,0 +1,86 @@ +MediaTek T-PHY binding +-------------------------- + +T-phy controller supports physical layer functionality for a number of +controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. + +Required properties (controller (parent) node): + - compatible : should be one of + "mediatek,generic-tphy-v1" + - clocks : (deprecated, use port's clocks instead) a list of phandle + + clock-specifier pairs, one for each entry in clock-names + - clock-names : (deprecated, use port's one instead) must contain + "u3phya_ref": for reference clock of usb3.0 analog phy. + +Required nodes : a sub-node is required for each port the controller + provides. Address range information including the usual + 'reg' property is used inside these nodes to describe + the controller's topology. + +Optional properties (controller (parent) node): + - reg : offset and length of register shared by multiple ports, + exclude port's private register. + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate + calibrate + - mediatek,src-coef : coefficient for slew rate calibrate, depends on + SoC process + +Required properties (port (child) node): +- reg : address and length of the register set for the port. +- clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names +- clock-names : must contain + "ref": 48M reference clock for HighSpeed analog phy; and 26M + reference clock for SuperSpeed analog phy, sometimes is + 24M, 25M or 27M, depended on platform. +- #phy-cells : should be 1 (See second example) + cell after port phandle is phy type from: + - PHY_TYPE_USB2 + - PHY_TYPE_USB3 + - PHY_TYPE_PCIE + - PHY_TYPE_SATA + +Example: + + u3phy2: usb-phy@1a244000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a244000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0x1a244800 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0x1a244900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + +Specifying phy control of devices +--------------------------------- + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the phy port node and a device type; +phy-names for each port are optional. + +Example: + +#include + +usb30: usb@11270000 { + ... + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + phy-names = "usb2-0", "usb3-0"; + ... +};