From patchwork Thu Aug 22 10:26:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1151465 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46Dgm32ZGNz9s3Z for ; Thu, 22 Aug 2019 20:30:43 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 18F39C220A3; Thu, 22 Aug 2019 10:28:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 64765C22061; Thu, 22 Aug 2019 10:27:44 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 91C0DC2208D; Thu, 22 Aug 2019 10:27:30 +0000 (UTC) Received: from mxwww.masterlogin.de (mxwww.masterlogin.de [95.129.51.220]) by lists.denx.de (Postfix) with ESMTPS id 60691C22085 for ; Thu, 22 Aug 2019 10:27:28 +0000 (UTC) Received: from mxout2.routing.net (unknown [192.168.10.82]) by new.mxwww.masterlogin.de (Postfix) with ESMTPS id A6F0196D3F; Thu, 22 Aug 2019 10:27:27 +0000 (UTC) Received: from mxbox3.masterlogin.de (unknown [192.168.10.253]) by mxout2.routing.net (Postfix) with ESMTP id 0B21C648E5; Thu, 22 Aug 2019 10:27:28 +0000 (UTC) Received: from localhost.localdomain (fttx-pool-217.61.154.89.bambit.de [217.61.154.89]) by mxbox3.masterlogin.de (Postfix) with ESMTPSA id 71CFA360452; Thu, 22 Aug 2019 12:27:27 +0200 (CEST) From: Frank Wunderlich To: u-boot@lists.denx.de Date: Thu, 22 Aug 2019 12:26:53 +0200 Message-Id: <20190822102656.4993-6-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190822102656.4993-1-frank-w@public-files.de> References: <20190822102656.4993-1-frank-w@public-files.de> Cc: Ryder Lee , GSS_MTK_Uboot_upstream Subject: [U-Boot] [PATCH v4 5/8] dt-bindings: pcie: add a document for MT7623 PCIe controller X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This adds a document for MT7623 PCIe controller. Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- changes since v3: none changes since v2: dt-bindings added with v3 --- .../pci/mediatek-pcie.txt | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 doc/device-tree-bindings/pci/mediatek-pcie.txt diff --git a/doc/device-tree-bindings/pci/mediatek-pcie.txt b/doc/device-tree-bindings/pci/mediatek-pcie.txt new file mode 100644 index 0000000000..2f9f549b7a --- /dev/null +++ b/doc/device-tree-bindings/pci/mediatek-pcie.txt @@ -0,0 +1,122 @@ +MediaTek Gen2 PCIe controller + +Required properties: +- compatible: Should contain one of the following strings: + "mediatek,mt7623-pcie" +- device_type: Must be "pci" +- reg: Base addresses and lengths of the PCIe subsys and root ports. +- reg-names: Names of the above areas to use during resource lookup. +- #address-cells: Address representation for root ports (must be 3) +- #size-cells: Size representation for root ports (must be 2) +- clocks: Must contain an entry for each entry in clock-names. +- clock-names: + Mandatory entries: + - sys_ckN :transaction layer and data link layer clock + Required entries for MT7623: + - free_ck :for reference clock of PCIe subsys + where N starting from 0 to one less than the number of root ports. +- phys: List of PHY specifiers (used by generic PHY framework). +- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the + number of PHYs as specified in *phys* property. +- power-domains: A phandle and power domain specifier pair to the power domain + which is responsible for collapsing and restoring power to the peripheral. +- bus-range: Range of bus numbers associated with this controller. +- ranges: Ranges for the PCI memory and I/O regions. + +Required properties for MT7623: +- #interrupt-cells: Size representation for interrupts (must be 1) +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- resets: Must contain an entry for each entry in reset-names. +- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the + number of root ports. + +In addition, the device tree node must have sub-nodes describing each +PCIe port interface, having the following mandatory properties: + +Required properties: +- device_type: Must be "pci" +- reg: Only the first four bytes are used to refer to the correct bus number + and device number. +- #address-cells: Must be 3 +- #size-cells: Must be 2 +- #interrupt-cells: Must be 1 +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties + Please refer to the standard PCI bus binding document for a more detailed + explanation. +- ranges: Sub-ranges distributed from the PCIe controller node. An empty + property is sufficient. + +Examples for MT7623: + + hifsys: syscon@1a000000 { + compatible = "mediatek,mt7623-hifsys", + "syscon"; + reg = <0x1a000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + pcie: pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0x1a140000 0x1000>, /* PCIe shared registers */ + <0x1a142000 0x1000>, /* Port0 registers */ + <0x1a143000 0x1000>, /* Port1 registers */ + <0x1a144000 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys HIFSYS_PCIE0_RST>, + <&hifsys HIFSYS_PCIE1_RST>, + <&hifsys HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>, + <&pcie2_phy PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 /* I/O space */ + 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; /* memory space */ + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + }; + };