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Tue, 06 Aug 2019 17:09:08 +0200 From: Frank Wunderlich To: Albert Aribaud , Ryder Lee , Weijie Gao , GSS_MTK_Uboot_upstream , Frank Wunderlich , Simon Glass , Mark Lee , Oleksandr Rybalko , Christian Gmeiner , Tuomas Tynkkynen , Prabhakar Kushwaha , Hou Zhiqiang , Marek Vasut , Stefan Roese , Bin Meng , Bao Xiaowei , Jean-Jacques Hiblot , Neil Armstrong , Ramon Fried , Daniel Schwierzeck , u-boot@lists.denx.de Date: Tue, 6 Aug 2019 17:08:50 +0200 Message-Id: <20190806150852.5527-7-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190806150852.5527-1-frank-w@public-files.de> References: <20190806150852.5527-1-frank-w@public-files.de> X-Provags-ID: V03:K1:ThxfnUDQrPo5l6OrqLe5QGo3zbI5QeboUj6IebeuzQrSCYw9SqW hYxza4rczOCPomRMM3io8u/d596UivvXfybW+OYa506i4g8HdTbW9WT+/XPsGFM/sfF1R6c 7FzRDxGtVndQRe7GZz9v7XuwuUN4hq/GIIhzOSPZI8pSmqLSXf40tmEx30YS0Hlif8M/j8c ZZY2YR+6CDUQrYGnb5F1w== X-UI-Out-Filterresults: notjunk:1; V03:K0:W8jfFoWM6zY=:awm7O9Bw+7x642mqMcY4iA yA0KdZxuZUtGn8j3PlzDvrSOuFcbOtP3DuTVOtAmlWm4sZGJoRWclMtm/Ojjib/63QM8sFaok m3khDn7eHJ1Xzb8yqraGrYPF/y/eQDjzwqS3Nc//FVoi1KQv/VMvA6MBcQ24qugxLUVeGaU+4 1jaKnFJqO1NMs4D0Fs4NDQHWUpdYBo45UBfp+WtC+0UKrCFgIiL3adnDg1fZL8QqrW4+Du/fT suWOUJOMNaGD/HYEG6ghXTtFnZiqctfBYNjEAtuJFep30FAEY62ANuy1OOWWhNmnmFujrfH3I ZlCM7hG4PE2bSai0EuzbP+D0vs2L/pjiwfsqCehG5ZL2KvNQQFJ5eyS5tl3dIlSH2Gt8hNHEh QMTPhkglhQLTqN3krmeKEGCAUlP4qgUl7eOXO6NaFQ5r+npZH6z8GuPGJ3LSuT1pLfMpLyKDp NnddkzFXdi4C5HyiApu346LEoKvy4QHyK8qtMnLg2dzyUouOAZFiS9wFfrtGZzD6E6GMHI0u1 PGVfe0ed9fo92Lw7pedIfXR+iOvVhdjt6FCMlG/R1fqbnBQ6YxboRnUN+KyL6wn6xoz8K01OG WVPfrk6JtB/VenyO42d83yf/Z7b9hBGF3tgntEZBJ4vpNu+296oEcV1gvFBKPXyuY7Ym84J/a YL51aNhqkfLUkXRq1SF8FKlElElmZMi3T/zGCzpdeDCpdpWdZ7h/dMy6xh5OmLvbIuFsoTKNn 9RDXV9b3u6YSM6YKtvYGwXywXEcg/xU3JW1Z6WWimyGE88Bm/S0qFj/JEq1EwR8mhDRbs4q7+ ZumT2Cs5JrsrZ2KOXofg4mseEj09E3cDA5auNz9WwmsHsZEPdff574NXnLOUnsTewJKv7dwuC AZ21PUkYQosTHzIXIxaARXZ7PS1ykF10q/ww78gW++MewOQx6G3DA9MbGD7ki9w2yR8wldYv8 BGAyAvC/JduQMITQxU3w5QeEGueBTaX6s9F7G1vSEmofz+HdobjcX5AGYqI9vJp9ydhzIxJvn u++oKJLJDjx0KAu3VrIaBlaHRZ2YEjVtY17nYFR+kMTUflNz8q9fZcfZ0Z0oSutZeREb1O7J6 l9A+BqCnxjR1OAelh0S9qcZMcpzi1juswCQ9Uchz5ubWSUs0t6QOcYlcQ== Subject: [U-Boot] [PATCH v3 6/8] dt-bindings: phy: add a document for MediaTek tphy X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This adds a document for tphy which supports physical layer functionality for a number of controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. changes since v2: dt-bindings added with v3 Signed-off-by: Ryder Lee Signed-off-by: Frank Wunderlich --- doc/device-tree-bindings/phy/phy-mtk-tphy.txt | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 doc/device-tree-bindings/phy/phy-mtk-tphy.txt -- 2.17.1 diff --git a/doc/device-tree-bindings/phy/phy-mtk-tphy.txt b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt new file mode 100644 index 0000000000..037c5a4be5 --- /dev/null +++ b/doc/device-tree-bindings/phy/phy-mtk-tphy.txt @@ -0,0 +1,86 @@ +MediaTek T-PHY binding +-------------------------- + +T-phy controller supports physical layer functionality for a number of +controllers on MediaTek SoCs, such as, USB2.0, USB3.0, PCIe, and SATA. + +Required properties (controller (parent) node): + - compatible : should be one of + "mediatek,generic-tphy-v1" + - clocks : (deprecated, use port's clocks instead) a list of phandle + + clock-specifier pairs, one for each entry in clock-names + - clock-names : (deprecated, use port's one instead) must contain + "u3phya_ref": for reference clock of usb3.0 analog phy. + +Required nodes : a sub-node is required for each port the controller + provides. Address range information including the usual + 'reg' property is used inside these nodes to describe + the controller's topology. + +Optional properties (controller (parent) node): + - reg : offset and length of register shared by multiple ports, + exclude port's private register. + - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate + calibrate + - mediatek,src-coef : coefficient for slew rate calibrate, depends on + SoC process + +Required properties (port (child) node): +- reg : address and length of the register set for the port. +- clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names +- clock-names : must contain + "ref": 48M reference clock for HighSpeed analog phy; and 26M + reference clock for SuperSpeed analog phy, sometimes is + 24M, 25M or 27M, depended on platform. +- #phy-cells : should be 1 (See second example) + cell after port phandle is phy type from: + - PHY_TYPE_USB2 + - PHY_TYPE_USB3 + - PHY_TYPE_PCIE + - PHY_TYPE_SATA + +Example: + + u3phy2: usb-phy@1a244000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a244000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0x1a244800 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0x1a244900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + +Specifying phy control of devices +--------------------------------- + +Device nodes should specify the configuration required in their "phys" +property, containing a phandle to the phy port node and a device type; +phy-names for each port are optional. + +Example: + +#include + +usb30: usb@11270000 { + ... + phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; + phy-names = "usb2-0", "usb3-0"; + ... +};