From patchwork Sun Aug 4 17:23:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1141817 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="EiVkBArX"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 461ns26dNZz9sMr for ; Mon, 5 Aug 2019 03:27:18 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id A432BC21DCA; Sun, 4 Aug 2019 17:25:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A6B26C21E08; Sun, 4 Aug 2019 17:25:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 4E4B1C21DFD; Sun, 4 Aug 2019 17:24:38 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.22]) by lists.denx.de (Postfix) with ESMTPS id D077AC21E18 for ; Sun, 4 Aug 2019 17:24:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564939444; bh=fUI0hYG88ARs2nUIjumiLMHryqThJg+zR291mNfBy0I=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=EiVkBArX+4tuTMcFfARoK9ptx84F8XLR5KgxFjLginjN0L2CBZHx2uoq8TfK+DNvJ VPGKgQiEWRyibbz8IlpC3kpgJugOurPjU5YipbmmyUV2y1gw4Yr9JzVt20WpFPchWe 3qVjtn3e7Ab+Owzm56GMdw2axMIbKNk2/I/XH2PY= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.144.189]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0MY75A-1hq0mp3Y8G-00UoN9; Sun, 04 Aug 2019 19:24:04 +0200 From: Frank Wunderlich To: Albert Aribaud , Christian Gmeiner , Daniel Schwierzeck , Frank Wunderlich , GSS_MTK_Uboot_upstream , Hou Zhiqiang , Jean-Jacques Hiblot , Marek Vasut , Mark Lee , Neil Armstrong , Oleksandr Rybalko , Prabhakar Kushwaha , Ramon Fried , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Sun, 4 Aug 2019 19:23:39 +0200 Message-Id: <20190804172342.5225-4-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190804172342.5225-1-frank-w@public-files.de> References: <20190804172342.5225-1-frank-w@public-files.de> X-Provags-ID: V03:K1:sorMS/NEG3tNj9Bclr1oNajG9Qe0rnIWWRELIwUSC79DguvvMY/ Cn83dF9KB9kUoNG10rKUtT7ZO3Qwn6bDKKSQK+oOqAIkaEKeMW9Hvq0evyB57S2BRjXuj+X 6sWZDU7NRmxy9binZ/+VdhlKz26pJNQi00q1+qdJHDhzuMx0NxvW6eZBNaewGUfR9vklKhQ 2s2v3eypiYZr5v7bRjp7A== X-UI-Out-Filterresults: notjunk:1; V03:K0:RWGLY8KFp+I=:OnOLuYth4cADz8ROc6Cmij hXTJe69OGsY+JbCXXGhGE6GdAQzHTtip8fSw0wmFmyJADl488RvY2dB5a1dR64EzsRrKCWS3B lfsJGWNIDyxaJBIkznkepcOtAJmWj3/EM53eHDArRw2dNqYP0OhkZKdD8g42cqjcGAf8YYZYL A2f+WgkZjSas+1UWkLgJSfSnHWjFWYkH462oh3MwzanWhILeeq/zcjLOt33R8zUeigEWcgd9D RXkaOWXKX2ujceiFWOPqo+DEyWURoywbVMt8zXTkkjYCXYV8JqjG3P9qNssK8iU2FRas3VsRF IBu6QhhVCt9Ao4sV2zgrstU9QUT0Gd+uiHAPx6hrhdvyWqP4RrBwsGTtgsdPj0WKy2T3E0D0q EmzEYpBpoVFr7ThFBmKMHjTIakgxqZKB98R/WKCbIGOjtQiz+0kwFwdszbDWlveq6EVepy+R2 jHhujRNvXwGB4k6zfY6zkauXca4KqbcQmAXE05TzDrZ0jVjU4nntja+vTrJoGKNYZe7g18f56 920G1mFEe/WpRdD9dNRlhCHZmF+/Enp12BbLk3A/S6WIqeMECqH31cNkcVqBv7kuYP1HMi6L5 sc3XhcTIzWsYkUA4Av6ppVP58fea0lwKvXMWUT3IfVra2F2tW9I1bJTFsRH+4uZ8AZYrB3S25 y5od9QxEImhfs75PNZiLZPBZKAu6WTXgbhg68WRieM8eiekCSQXuQ/uLw/W6OAhlJcJCs0Wtk 3XSsabz3AHSyoctIy40tX8wtWqqn4XuQuAS5STQrVZ3bxyJLAHsXIoV92Q9/PZ0LMje2lREWP HpVi7McglGugZVh2quSGDFEaSV4n3ui71NE+Sp1JrdLCD16S45n4OGHGYhB2P6V3bLXyPZTo8 xc0rRcReM+u07Z3WuBSoftsgQ6y2F87d+K/Kr+ZlcNpBTVuPKVtXpuY1undER5Sqa81QxSiyF bOhcaTLxcO1qARJKHGym0KHZ/ek8HRl0IIbx3mSufxk4p/sJ6dTpV1Mt5apZulbYeDOshP2Fu C5rKATFpD2D9oGmU3pK5MImfR4GcZumy1zD3uUHYvf++iaXSGxusHsDTZ3kBgyvRWxHk9X6xg Dm5JV5HCwiHNSCroiV/hOdG1WbD+uc9p7awUQZsuI7EgPniH/ceTmc6uA== Subject: [U-Boot] [PATCH v2 3/6] arm: dts: add PCIe controller for MT7623 SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This adds PCIe and its PHY nodes for MT7623. Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Ryder Lee --- arch/arm/dts/mt7623.dtsi | 128 +++++++++++++++++++++++ arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 29 +++++ 2 files changed, 157 insertions(+) -- 2.17.1 diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi index 64079c61bf..3a868ea2ee 100644 --- a/arch/arm/dts/mt7623.dtsi +++ b/arch/arm/dts/mt7623.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include "skeleton.dtsi" @@ -255,6 +256,133 @@ #reset-cells = <1>; }; + pcie: pcie@1a140000 { + compatible = "mediatek,mt7623-pcie"; + device_type = "pci"; + reg = <0x1a140000 0x1000>, /* PCIe shared registers */ + <0x1a142000 0x1000>, /* Port0 registers */ + <0x1a143000 0x1000>, /* Port1 registers */ + <0x1a144000 0x1000>; /* Port2 registers */ + reg-names = "subsys", "port0", "port1", "port2"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xf800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>, + <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>, + <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + clocks = <&topckgen CLK_TOP_ETHIF_SEL>, + <&hifsys CLK_HIFSYS_PCIE0>, + <&hifsys CLK_HIFSYS_PCIE1>, + <&hifsys CLK_HIFSYS_PCIE2>; + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2"; + resets = <&hifsys HIFSYS_PCIE0_RST>, + <&hifsys HIFSYS_PCIE1_RST>, + <&hifsys HIFSYS_PCIE2_RST>; + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2"; + phys = <&pcie0_port PHY_TYPE_PCIE>, + <&pcie1_port PHY_TYPE_PCIE>, + <&u3port1 PHY_TYPE_PCIE>; + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; + power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>; + bus-range = <0x00 0xff>; + status = "disabled"; + ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 + 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; + + pcie@0,0 { + reg = <0x0000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + + pcie@1,0 { + reg = <0x0800 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + + pcie@2,0 { + reg = <0x1000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; + ranges; + status = "disabled"; + }; + }; + + pcie0_phy: pcie-phy@1a149000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a149000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie0_port: pcie-phy@1a149900 { + reg = <0x1a149900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + pcie1_phy: pcie-phy@1a14a000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a14a000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pcie1_port: pcie-phy@1a14a900 { + reg = <0x1a14a900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + + u3phy2: usb-phy@1a244000 { + compatible = "mediatek,generic-tphy-v1"; + reg = <0x1a244000 0x0700>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + u2port1: usb-phy@1a244800 { + reg = <0x1a244800 0x0100>; + clocks = <&topckgen CLK_TOP_USB_PHY48M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port1: usb-phy@1a244900 { + reg = <0x1a244900 0x0700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7623-ethsys", "syscon"; reg = <0x1b000000 0x1000>; diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts index 51628bb639..b0c86219b6 100644 --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts @@ -172,6 +172,13 @@ }; }; + pcie_default: pcie-default { + mux { + function = "pcie"; + groups = "pcie0_0_perst", "pcie1_0_perst"; + }; + }; + uart0_pins_a: uart0-default { mux { function = "uart"; @@ -201,6 +208,28 @@ }; }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_default>; + status = "okay"; + + pcie@0,0 { + status = "okay"; + }; + + pcie@1,0 { + status = "okay"; + }; +}; + +&pcie0_phy { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_a>;