From patchwork Sun Aug 4 17:23:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 1141812 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=public-files.de Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=gmx.net header.i=@gmx.net header.b="H6HNSIHI"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 461npJ5y05z9sMr for ; Mon, 5 Aug 2019 03:24:56 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 6A192C21D8E; Sun, 4 Aug 2019 17:24:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1747BC21D65; Sun, 4 Aug 2019 17:24:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 73A92C21D83; Sun, 4 Aug 2019 17:24:21 +0000 (UTC) Received: from mout.gmx.net (mout.gmx.net [212.227.17.20]) by lists.denx.de (Postfix) with ESMTPS id D9894C21C51 for ; Sun, 4 Aug 2019 17:24:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1564939441; bh=LNSkSBfAEc6wPGEU0YLiKKmmWssKDA2Us1Jou9ICXE8=; h=X-UI-Sender-Class:From:To:Subject:Date:In-Reply-To:References; b=H6HNSIHIsfhkhYCF5QylpOawNy8D2y9CxYBNlv8eqyj2S1EBSnQ5r+7deO8zUNQa+ Xi4/HoC/p/LOKyVjuhmoCIsqpD1FFlyt+xpagLQXMd3ZqxanVmhPmgOvEG348D4iWm 5FzOXL7pd3+btL3N8VvrJyDapYkZj3SR+h/UcMmo= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from localhost.localdomain ([217.61.144.189]) by mail.gmx.com (mrgmx103 [212.227.17.168]) with ESMTPSA (Nemesis) id 0Lu7ty-1iJJOp01n4-011Pd7; Sun, 04 Aug 2019 19:24:01 +0200 From: Frank Wunderlich To: Albert Aribaud , Christian Gmeiner , Daniel Schwierzeck , Frank Wunderlich , GSS_MTK_Uboot_upstream , Hou Zhiqiang , Jean-Jacques Hiblot , Marek Vasut , Mark Lee , Neil Armstrong , Oleksandr Rybalko , Prabhakar Kushwaha , Ramon Fried , Ryder Lee , Simon Glass , Stefan Roese , Tuomas Tynkkynen , u-boot@lists.denx.de, Weijie Gao Date: Sun, 4 Aug 2019 19:23:37 +0200 Message-Id: <20190804172342.5225-2-frank-w@public-files.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190804172342.5225-1-frank-w@public-files.de> References: <20190804172342.5225-1-frank-w@public-files.de> X-Provags-ID: V03:K1:rrZE51PNbtXT3ri8Ue2IaK/pRfAl/nBcIvcx/pdq44goFehotA1 cnlRzV43C5rjWzN3GO6e+Ztg2xDunvae9987oKdeP29ASqSuSmiGJiW8PuCR054VerUrT9A a3HGpqiuHDXSSsI5RPycjB/AVFeF9FYekD/gp2nMjOMrhkXfhs0scWhpd3mY4kKkPEdqyHp LsFR5oNvUSxJEEI+XnWaw== X-UI-Out-Filterresults: notjunk:1; V03:K0:vt4UiGpHFbU=:zY17w9qzJ7Xr1pNZwnTxAK 00CqTSBNhyNzufSf+DsJCvRwprfrRqGwgzPGqnD9sm8RhMzbutxfkkn602VEaWDwhBGPhwlgj A60fVNjUDalz0M0b8yFxlcEmRwvvfeUdeLgdjEqvBPKhS524nDJr4y7s7c1WIxmULUbLekvQe +kHo4huxcoDBELnXsXpARdqKUOOmXVaxxcsD5watw9v8owIyYyDb4ZyC6M343PO9XcMFb72Ir ZAkMkstP7KDbW9ibeEKT5Q/1KlcH8tt9yyntMVkdtl2ZAgxcdsUCH2++PPSua0FDYo1nEN+E4 cHykaFFI17QUhoyoifwINKLvtu7TDJz/tXGLOk3u0qS1kXKJW1auOtRFcp5FiUkERrY7Qy8Uk PqO9t/YfTtTERuoHZbqzR0Ir7FT7Q/5QqI0hCN/EDEZwKlXAzzYBGm+jon0DzdbOY/rUJ8MOQ NnrRdDbICLiaORfQvFV35OzEHosTxhSONllDWz2Nv3SBzCzZgMQwcgK3mGlx5bkcQDiJQORWN cnaT6vh102Z37vepeXZDVqSq1Sngck3yFhvXthkYeE2xWugczCPd0D99JVFXg864+dsadF0Uo 9g5btWnfLhrlTHRKVUk61aEeDFz2jg1hqMc2cZ/NfFDIp40ZicBEHS+1iKRXN9Y3upQmM5H0W zjL7DYvpCJH+SHZPzJv0C9H8Lx572dHkJHqZVjg8NaEKs0mNKRNCxaT+tSBh2WDrtHJ591Zsg 2XmjBCO3PEY8o6cWXLCdy64+hDG1aJji5nSQHwHEqo7Pq2+eVSYGPA4LbblLUXbFxGy5Dq/Au gbiJdc6Z7+Uo9EpXGtiaWjRh4Y6IUR1bSmlDPAmAVVzeFTCwQFeSvG0NR3wYqP98vITlW6n4C RbeddLNMdLH/PBmV3AWTle1QBPows5FG9s/7cfvFwR8xLi59LR7z1BjZfrINLeh9Lh8epz7AK v7GKFULfj0s52mNcCxfQMS9jTKOxtvoClm9Q2A5Py+f32SF8cAi86ebA6G5c0k3spmc973hNc 1bINdp4PNhDvlxFZsgejqhUCZAINrac68i1+a95qDm8Z9Dk7kZASxTWDuomp56hZlHUJGFkAC Iam009znkzyVEO2hB6P1ETYcR0xIWWNIJEL37eLfDVFA92O4srNlR5EWA== Subject: [U-Boot] [PATCH v2 1/6] pci: mediatek: add PCIe controller support for MT7623 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Ryder Lee This adds PCIe controller support for MT7623. Tested-by: Frank Wunderlich Signed-off-by: Frank Wunderlich Signed-off-by: Ryder Lee --- drivers/pci/Kconfig | 8 + drivers/pci/Makefile | 1 + drivers/pci/pcie_mediatek.c | 292 ++++++++++++++++++++++++++++++++++++ 3 files changed, 301 insertions(+) create mode 100644 drivers/pci/pcie_mediatek.c -- 2.17.1 diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 3fe38f7315..6f19471ae7 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -145,4 +145,12 @@ config PCI_MVEBU Say Y here if you want to enable PCIe controller support on Armada XP/38x SoCs. +config PCIE_MEDIATEK + bool "MediaTek PCIe controller" + depends on DM_PCI + depends on ARCH_MEDIATEK + help + Say Y here if you want to enable PCIe controller support on + MediaTek SoCs. + endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index b5ebd50c85..7093d63918 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -38,3 +38,4 @@ obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie_layerscape_gen4.o \ pcie_layerscape_gen4_fixup.o obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o obj-$(CONFIG_PCIE_INTEL_FPGA) += pcie_intel_fpga.o +obj-$(CONFIG_PCIE_MEDIATEK) += pcie_mediatek.o diff --git a/drivers/pci/pcie_mediatek.c b/drivers/pci/pcie_mediatek.c new file mode 100644 index 0000000000..3f24060d26 --- /dev/null +++ b/drivers/pci/pcie_mediatek.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MediaTek PCIe host controller driver. + * + * Copyright (c) 2017-2019 MediaTek Inc. + * Author: Ryder Lee + * Honghui Zhang + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PCIe shared registers */ +#define PCIE_SYS_CFG 0x00 +#define PCIE_INT_ENABLE 0x0c +#define PCIE_CFG_ADDR 0x20 +#define PCIE_CFG_DATA 0x24 + +/* PCIe per port registers */ +#define PCIE_BAR0_SETUP 0x10 +#define PCIE_CLASS 0x34 +#define PCIE_LINK_STATUS 0x50 + +#define PCIE_PORT_INT_EN(x) BIT(20 + (x)) +#define PCIE_PORT_PERST(x) BIT(1 + (x)) +#define PCIE_PORT_LINKUP BIT(0) +#define PCIE_BAR_MAP_MAX GENMASK(31, 16) + +#define PCIE_BAR_ENABLE BIT(0) +#define PCIE_REVISION_ID BIT(0) +#define PCIE_CLASS_CODE (0x60400 << 8) +#define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \ + ((((regn) >> 8) & GENMASK(3, 0)) << 24)) +#define PCIE_CONF_ADDR(regn, bdf) \ + (PCIE_CONF_REG(regn) | (bdf)) + +/* MediaTek specific configuration registers */ +#define PCIE_FTS_NUM 0x70c +#define PCIE_FTS_NUM_MASK GENMASK(15, 8) +#define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8) + +#define PCIE_FC_CREDIT 0x73c +#define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16)) +#define PCIE_FC_CREDIT_VAL(x) ((x) << 16) + +struct mtk_pcie_port { + void __iomem *base; + struct list_head list; + struct mtk_pcie *pcie; + struct reset_ctl reset; + struct clk sys_ck; + struct phy phy; + u32 slot; +}; + +struct mtk_pcie { + void __iomem *base; + struct clk free_ck; + struct list_head ports; +}; + +static int mtk_pcie_config_address(struct udevice *udev, pci_dev_t bdf, + uint offset, void **paddress) +{ + struct mtk_pcie *pcie = dev_get_priv(udev); + + writel(PCIE_CONF_ADDR(offset, bdf), pcie->base + PCIE_CFG_ADDR); + *paddress = pcie->base + PCIE_CFG_DATA + (offset & 3); + + return 0; +} + +static int mtk_pcie_read_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + return pci_generic_mmap_read_config(bus, mtk_pcie_config_address, + bdf, offset, valuep, size); +} + +static int mtk_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + return pci_generic_mmap_write_config(bus, mtk_pcie_config_address, + bdf, offset, value, size); +} + +static const struct dm_pci_ops mtk_pcie_ops = { + .read_config = mtk_pcie_read_config, + .write_config = mtk_pcie_write_config, +}; + +static void mtk_pcie_port_free(struct mtk_pcie_port *port) +{ + list_del(&port->list); + free(port); +} + +static int mtk_pcie_startup_port(struct mtk_pcie_port *port) +{ + struct mtk_pcie *pcie = port->pcie; + u32 slot = PCI_DEV(port->slot << 11); + u32 val; + int err; + + /* assert port PERST_N */ + val = readl(pcie->base + PCIE_SYS_CFG); + val |= PCIE_PORT_PERST(port->slot); + writel(val, pcie->base + PCIE_SYS_CFG); + + /* de-assert port PERST_N */ + val = readl(pcie->base + PCIE_SYS_CFG); + val &= ~PCIE_PORT_PERST(port->slot); + writel(val, pcie->base + PCIE_SYS_CFG); + + /* 100ms timeout value should be enough for Gen1/2 training */ + err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, + !!(val & PCIE_PORT_LINKUP), 100000); + if (err) + return -ETIMEDOUT; + + /* disable interrupt */ + val = readl(pcie->base + PCIE_INT_ENABLE); + val &= ~PCIE_PORT_INT_EN(port->slot); + writel(val, pcie->base + PCIE_INT_ENABLE); + + /* map to all DDR region. We need to set it before cfg operation. */ + writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE, + port->base + PCIE_BAR0_SETUP); + + /* configure class code and revision ID */ + writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); + + /* configure FC credit */ + writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot), + pcie->base + PCIE_CFG_ADDR); + val = readl(pcie->base + PCIE_CFG_DATA); + val &= ~PCIE_FC_CREDIT_MASK; + val |= PCIE_FC_CREDIT_VAL(0x806c); + writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, slot), + pcie->base + PCIE_CFG_ADDR); + writel(val, pcie->base + PCIE_CFG_DATA); + + /* configure RC FTS number to 250 when it leaves L0s */ + writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR); + val = readl(pcie->base + PCIE_CFG_DATA); + val &= ~PCIE_FTS_NUM_MASK; + val |= PCIE_FTS_NUM_L0(0x50); + writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, slot), pcie->base + PCIE_CFG_ADDR); + writel(val, pcie->base + PCIE_CFG_DATA); + + return 0; +} + +static void mtk_pcie_enable_port(struct mtk_pcie_port *port) +{ + int err; + + err = clk_enable(&port->sys_ck); + if (err) + goto exit; + + err = reset_assert(&port->reset); + if (err) + goto exit; + + err = reset_deassert(&port->reset); + if (err) + goto exit; + + err = generic_phy_init(&port->phy); + if (err) + goto exit; + + err = generic_phy_power_on(&port->phy); + if (err) + goto exit; + + if (!mtk_pcie_startup_port(port)) + return; + + pr_err("Port%d link down\n", port->slot); +exit: + mtk_pcie_port_free(port); +} + +static int mtk_pcie_parse_port(struct udevice *dev, u32 slot) +{ + struct mtk_pcie *pcie = dev_get_priv(dev); + struct mtk_pcie_port *port; + char name[10]; + int err; + + port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + snprintf(name, sizeof(name), "port%d", slot); + port->base = dev_remap_addr_name(dev, name); + if (!port->base) + return -ENOENT; + + snprintf(name, sizeof(name), "sys_ck%d", slot); + err = clk_get_by_name(dev, name, &port->sys_ck); + if (err) + return err; + + err = reset_get_by_index(dev, slot, &port->reset); + if (err) + return err; + + err = generic_phy_get_by_index(dev, slot, &port->phy); + if (err) + return err; + + port->slot = slot; + port->pcie = pcie; + + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &pcie->ports); + + return 0; +} + +static int mtk_pcie_probe(struct udevice *dev) +{ + struct mtk_pcie *pcie = dev_get_priv(dev); + struct mtk_pcie_port *port, *tmp; + ofnode subnode; + int err; + + INIT_LIST_HEAD(&pcie->ports); + + pcie->base = dev_remap_addr_name(dev, "subsys"); + if (!pcie->base) + return -ENOENT; + + err = clk_get_by_name(dev, "free_ck", &pcie->free_ck); + if (err) + return err; + + /* enable top level clock */ + err = clk_enable(&pcie->free_ck); + if (err) + return err; + + dev_for_each_subnode(subnode, dev) { + struct fdt_pci_addr addr; + u32 slot = 0; + + if (!ofnode_is_available(subnode)) + continue; + + err = ofnode_read_pci_addr(subnode, 0, "reg", &addr); + if (err) + return err; + + slot = PCI_DEV(addr.phys_hi); + + err = mtk_pcie_parse_port(dev, slot); + if (err) + return err; + } + + /* enable each port, and then check link status */ + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + mtk_pcie_enable_port(port); + + return 0; +} + +static const struct udevice_id mtk_pcie_ids[] = { + { .compatible = "mediatek,mt7623-pcie", }, + { } +}; + +U_BOOT_DRIVER(pcie_mediatek) = { + .name = "pcie_mediatek", + .id = UCLASS_PCI, + .of_match = mtk_pcie_ids, + .ops = &mtk_pcie_ops, + .probe = mtk_pcie_probe, + .priv_auto_alloc_size = sizeof(struct mtk_pcie), +};