From patchwork Sun Jul 28 15:57:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 1138033 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45xSH73M7Nz9s7T for ; Mon, 29 Jul 2019 02:01:23 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 2B10BC21E13; Sun, 28 Jul 2019 15:59:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 389ECC21DC1; Sun, 28 Jul 2019 15:59:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CD8A4C21DFA; Sun, 28 Jul 2019 15:58:00 +0000 (UTC) Received: from mail-edgeS23.fraunhofer.de (mail-edges23.fraunhofer.de [153.97.7.23]) by lists.denx.de (Postfix) with ESMTPS id 4C16DC21DEC for ; Sun, 28 Jul 2019 15:57:58 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2EoBQB1xT1d/xwBYJllHAEBAQQBAQcEAQGBZ4IXgT8BHzyNGogai2ORKAkBAQEBAQEBAQEILwEBhEACgmMjOBMBAwEBBQEBAQEGAgJphR4MhUwGMgFGEFEhHBoGDgWDIoFrAxwBqz6IBw1fgUgJAYEqhwmEV4FXP4EQAYNQghqIDQSOSYVTlhtABwKBOWNdBI88g2sMG400ilqWeopCg32BZyKBWDMaJIM7gk4Xg0eKXD0BMgGPDwEB X-IPAS-Result: A2EoBQB1xT1d/xwBYJllHAEBAQQBAQcEAQGBZ4IXgT8BHzyNGogai2ORKAkBAQEBAQEBAQEILwEBhEACgmMjOBMBAwEBBQEBAQEGAgJphR4MhUwGMgFGEFEhHBoGDgWDIoFrAxwBqz6IBw1fgUgJAYEqhwmEV4FXP4EQAYNQghqIDQSOSYVTlhtABwKBOWNdBI88g2sMG400ilqWeopCg32BZyKBWDMaJIM7gk4Xg0eKXD0BMgGPDwEB X-IronPort-AV: E=Sophos;i="5.64,319,1559512800"; d="scan'208";a="12233468" Received: from mail-mtaka28.fraunhofer.de ([153.96.1.28]) by mail-edgeS23.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Jul 2019 17:57:57 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0BcBQCvxD1dfRBhWMBlHAEBAQQBAQcEAQGBZ4NWIDyNGpN9kSgJAQMBAQEBAQgvAQGEQAKDBTgTAQMBAQQBAQIBBhQBARY6hSUMhUsDAzIBRhBRIRwaBg4FgyKBawMdqz2IBw1fgUgJAYEqhwmGLj+BEAGDUIIaiA0EjkmFU5YbQAcCgTljXQSPPINrDBuNNIpalnqKQoN9gWcggVkzGiSDO4JOF4NHilw9AzABjw8BAQ X-IronPort-AV: E=Sophos;i="5.64,319,1559512800"; d="scan'208";a="20209993" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP12EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA28.fraunhofer.de with ESMTP/TLS/AES256-SHA; 28 Jul 2019 17:57:58 +0200 Received: from localhost.de (10.80.233.51) by FGDEMUCIMP12EXC.ads.fraunhofer.de (10.80.232.43) with Microsoft SMTP Server (TLS) id 14.3.439.0; Sun, 28 Jul 2019 17:57:56 +0200 From: Lukas Auer To: Date: Sun, 28 Jul 2019 17:57:22 +0200 Message-ID: <20190728155723.3412-11-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190728155723.3412-1-lukas.auer@aisec.fraunhofer.de> References: <20190728155723.3412-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24806.001 X-TM-AS-Result: No--9.133900-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Alistair Francis Subject: [U-Boot] [PATCH v2 10/11] riscv: qemu: add SPL configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add two new configurations (qemu-riscv{32,64}_spl_defconfig) with SPL enabled for RISC-V QEMU. QEMU does not require SPL to run U-Boot. The configurations are meant to help the development of SPL on RISC-V. The configurations enable RAM as the only SPL boot device. Images must be loaded at address 0x80200000. In the default boot flow, U-Boot SPL starts in machine mode, loads the OpenSBI FW_DYNAMIC firmware and U-Boot proper from the supplied FIT image, and starts OpenSBI. U-Boot proper is then started in supervisor mode by OpenSBI. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel --- Changes in v2: None board/emulation/qemu-riscv/Kconfig | 10 ++++++++++ board/emulation/qemu-riscv/MAINTAINERS | 2 ++ board/emulation/qemu-riscv/qemu-riscv.c | 17 +++++++++++++++++ configs/qemu-riscv32_spl_defconfig | 11 +++++++++++ configs/qemu-riscv64_spl_defconfig | 12 ++++++++++++ include/configs/qemu-riscv.h | 14 ++++++++++++++ 6 files changed, 66 insertions(+) create mode 100644 configs/qemu-riscv32_spl_defconfig create mode 100644 configs/qemu-riscv64_spl_defconfig diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 6cc7c31dc6..1928d6dda0 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -13,13 +13,21 @@ config SYS_CONFIG_NAME default "qemu-riscv" config SYS_TEXT_BASE + default 0x81200000 if SPL default 0x80000000 if !RISCV_SMODE default 0x80200000 if RISCV_SMODE && ARCH_RV64I default 0x80400000 if RISCV_SMODE && ARCH_RV32I +config SPL_TEXT_BASE + default 0x80000000 + +config SPL_OPENSBI_LOAD_ADDR + default 0x81000000 + config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select GENERIC_RISCV + select SUPPORT_SPL imply SYS_NS16550 imply VIRTIO_MMIO imply VIRTIO_NET @@ -43,5 +51,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply CMD_PCI imply E1000 imply NVME + imply SPL_RAM_SUPPORT + imply SPL_RAM_DEVICE endif diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS index c701c83d77..78969ed6bd 100644 --- a/board/emulation/qemu-riscv/MAINTAINERS +++ b/board/emulation/qemu-riscv/MAINTAINERS @@ -5,5 +5,7 @@ F: board/emulation/qemu-riscv/ F: include/configs/qemu-riscv.h F: configs/qemu-riscv32_defconfig F: configs/qemu-riscv32_smode_defconfig +F: configs/qemu-riscv32_spl_defconfig F: configs/qemu-riscv64_defconfig F: configs/qemu-riscv64_smode_defconfig +F: configs/qemu-riscv64_spl_defconfig diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index d6167aaef1..e04bd3001c 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -87,3 +88,19 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } + +#ifdef CONFIG_SPL +u32 spl_boot_device(void) +{ + /* RISC-V QEMU only supports RAM as SPL boot device */ + return BOOT_DEVICE_RAM; +} +#endif + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* boot using first FIT config */ + return 0; +} +#endif diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig new file mode 100644 index 0000000000..78e755b36a --- /dev/null +++ b/configs/qemu-riscv32_spl_defconfig @@ -0,0 +1,11 @@ +CONFIG_RISCV=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig new file mode 100644 index 0000000000..a3f5e29d58 --- /dev/null +++ b/configs/qemu-riscv64_spl_defconfig @@ -0,0 +1,12 @@ +CONFIG_RISCV=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index df22f780b0..69aa82d36a 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -8,6 +8,18 @@ #include +#ifdef CONFIG_SPL + +#define CONFIG_SPL_MAX_SIZE 0x00100000 +#define CONFIG_SPL_BSS_START_ADDR 0x84000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 + +#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 + +#endif + #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) @@ -22,6 +34,7 @@ /* Environment options */ #define CONFIG_ENV_SIZE SZ_128K +#ifndef CONFIG_SPL_BUILD #define BOOT_TARGET_DEVICES(func) \ func(QEMU, qemu, na) \ func(VIRTIO, virtio, 0) \ @@ -51,5 +64,6 @@ #define CONFIG_PREBOOT \ "setenv fdt_addr ${fdtcontroladdr};" \ "fdt addr ${fdtcontroladdr};" +#endif #endif /* __CONFIG_H */