From patchwork Mon Jun 3 21:05:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Igor Opaniuk X-Patchwork-Id: 1109482 X-Patchwork-Delegate: agust@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="JxvrmGLg"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45HnhM653wz9s3l for ; Tue, 4 Jun 2019 07:08:03 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 85410C21D4A; Mon, 3 Jun 2019 21:07:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 119DCC21E0F; Mon, 3 Jun 2019 21:06:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B8991C21E13; Mon, 3 Jun 2019 21:06:10 +0000 (UTC) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by lists.denx.de (Postfix) with ESMTPS id 865BDC21D4A for ; Mon, 3 Jun 2019 21:06:07 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id e16so5319049wrn.1 for ; Mon, 03 Jun 2019 14:06:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=DgI7vV3tYJdWGt2bKC6aDZLeDnNevs+T7Na/YIgUfo0=; b=JxvrmGLg7YthH/qewlaaBT9Hg92haPvPNmXYtyhY3s1diec9UVpG7UKL0MIr9X1Bl4 8OsNfumPgeAkHHyb0hpZBSB1NLH5G+sDnuA/bKH54ugs2bQ6MNFQJKJfTTKiFah1NiKu KujL/ZsPXaFJC3e7rUukPPy3vgeHYfHwINqC/b8W56LfDv4MehSyk5QB3csOEx6Ote2p Cc3Crnqe3pHvZiCWJ7xBKCS+QoMO0XeLlgenIgH9kxTuYjIJgvnOVFWkbYGbErysiwDj 05aBJv8WrlPK6kvih+M2y2jW3tbrr0yO+/8uU84nuvaHDCqPA62sMCm9eh/aCTQkv9ZD iBvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=DgI7vV3tYJdWGt2bKC6aDZLeDnNevs+T7Na/YIgUfo0=; b=Cg08RC9/Lm7VTFFU+z+T8tJ0DiuWMbha+Jyh/Cbh6FnziiydPaQaNpGIB7VRcogZxO tIlD/tr1QSAzfri0WEMdf4YHZjgUlNWy2+LprkaYClTAlhTBJxCUC2srRe2Nxyw+ApdW nadk0YyoHktVhyB3rFiziOQgaB07GwZUMwgDxSGbzNOE1ngNRNd2sbq09f5GUkeF/f6L q44FReCUcGS9z5XnGY6O5Ep7nbqxuPWbD1srGDAgMd2XuFUM7dU8Q9r83r+/ejP62hR7 cELY2wwi9hwF6DyeC27DRvvFM44hTHCKPPrOxg0IyUv4W/w0MYx0aZ8tbEMSbxnwrgQp 58hg== X-Gm-Message-State: APjAAAV+Z8EGUfhSQzvjjmK64jTZV8hR79iDHiRXCc5nlr5yQpZlL/hQ BL8VlUI20IBQAZXZnH3FFFXa6wzf X-Google-Smtp-Source: APXvYqzeCRvhr1JSPHwMSmBrGndom+o+v598Whs5m3qCgTFMz4qvNhz8rZbXM+18NrSSVAztc69klA== X-Received: by 2002:adf:bac5:: with SMTP id w5mr6549746wrg.124.1559595966920; Mon, 03 Jun 2019 14:06:06 -0700 (PDT) Received: from localhost ([194.105.145.90]) by smtp.gmail.com with ESMTPSA id e17sm2928541wrt.95.2019.06.03.14.06.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 03 Jun 2019 14:06:06 -0700 (PDT) From: Igor Opaniuk To: u-boot@lists.denx.de Date: Tue, 4 Jun 2019 00:05:58 +0300 Message-Id: <20190603210601.30857-4-igor.opaniuk@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190603210601.30857-1-igor.opaniuk@gmail.com> References: <20190603210601.30857-1-igor.opaniuk@gmail.com> Cc: max.krummenacher@toradex.com, Anson.Huang@nxp.com, otavio@ossystems.com.br, marcel.ziswiler@toradex.com, rui.silva@linaro.org, marcel@ziswiler.com, uboot-imx@nxp.com Subject: [U-Boot] [RFC 3/6] video: mxsfb: refactor video_hw_init() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Igor Opaniuk Refactor video_hw_init() function, and introduce an independent function for the common procedure of initialization. Currently video_hw_init() is only in charge of parsing configuration from env("videomode") and filling struct GraphicPanel, and new mxs_probe_common() does hw specific initialization (invocation of mxs_lcd_init() etc.) Signed-off-by: Igor Opaniuk --- drivers/video/mxsfb.c | 68 ++++++++++++++++++++++++++----------------- 1 file changed, 41 insertions(+), 27 deletions(-) diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 059fbf2b05..6e269409d6 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c @@ -128,6 +128,37 @@ static void mxs_lcd_init(u32 fb_addr, struct ctfb_res_modes *mode, int bpp) writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set); } +static int mxs_probe_common(struct ctfb_res_modes *mode, int bpp, void *fb) +{ + /* Start framebuffer */ + mxs_lcd_init((u32)fb, mode, bpp); + +#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM + /* + * If the LCD runs in system mode, the LCD refresh has to be triggered + * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid + * having to set this bit manually after every single change in the + * framebuffer memory, we set up specially crafted circular DMA, which + * sets the RUN bit, then waits until it gets cleared and repeats this + * infinitelly. This way, we get smooth continuous updates of the LCD. + */ + struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + + memset(&desc, 0, sizeof(struct mxs_dma_desc)); + desc.address = (dma_addr_t)&desc; + desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | + MXS_DMA_DESC_WAIT4END | + (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); + desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN; + desc.cmd.next = (uint32_t)&desc.cmd; + + /* Execute the DMA chain. */ + mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc); +#endif + + return 0; +} + void lcdif_power_down(void) { struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; @@ -151,8 +182,9 @@ void lcdif_power_down(void) void *video_hw_init(void) { int bpp = -1; + int ret = 0; char *penv; - void *fb; + void *fb = NULL; struct ctfb_res_modes mode; puts("Video: "); @@ -167,8 +199,7 @@ void *video_hw_init(void) bpp = video_get_params(&mode, penv); /* fill in Graphic device struct */ - sprintf(panel.modeIdent, "%dx%dx%d", - mode.xres, mode.yres, bpp); + sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp); panel.winSizeX = mode.xres; panel.winSizeY = mode.yres; @@ -211,31 +242,14 @@ void *video_hw_init(void) printf("%s\n", panel.modeIdent); - /* Start framebuffer */ - mxs_lcd_init(panel.frameAdrs, &mode, bpp); - -#ifdef CONFIG_VIDEO_MXS_MODE_SYSTEM - /* - * If the LCD runs in system mode, the LCD refresh has to be triggered - * manually by setting the RUN bit in HW_LCDIF_CTRL register. To avoid - * having to set this bit manually after every single change in the - * framebuffer memory, we set up specially crafted circular DMA, which - * sets the RUN bit, then waits until it gets cleared and repeats this - * infinitelly. This way, we get smooth continuous updates of the LCD. - */ - struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + ret = mxs_probe_common(&mode, bpp, fb); + if (ret) + goto dealloc_fb; - memset(&desc, 0, sizeof(struct mxs_dma_desc)); - desc.address = (dma_addr_t)&desc; - desc.cmd.data = MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN | - MXS_DMA_DESC_WAIT4END | - (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET); - desc.cmd.pio_words[0] = readl(®s->hw_lcdif_ctrl) | LCDIF_CTRL_RUN; - desc.cmd.next = (uint32_t)&desc.cmd; + return (void *)&panel; - /* Execute the DMA chain. */ - mxs_dma_circ_start(MXS_DMA_CHANNEL_AHB_APBH_LCDIF, &desc); -#endif +dealloc_fb: + free(fb); - return (void *)&panel; + return NULL; }