From patchwork Wed May 1 20:07:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Patra X-Patchwork-Id: 1093817 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="g7ZMhVMn"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44vTw04nPdz9sCJ for ; Thu, 2 May 2019 06:07:44 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id DDACAC21C8B; Wed, 1 May 2019 20:07:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0CF30C21C29; Wed, 1 May 2019 20:07:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5E641C21C29; Wed, 1 May 2019 20:07:38 +0000 (UTC) Received: from esa6.hgst.iphmx.com (esa6.hgst.iphmx.com [216.71.154.45]) by lists.denx.de (Postfix) with ESMTPS id 2E1A9C21BE5 for ; Wed, 1 May 2019 20:07:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1556741258; x=1588277258; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=eR35CmBcqfUKqlzQIsolVmNAinL08jqmXIaKHbCY5d0=; b=g7ZMhVMnN0H+KZwYYhlUTXwW0BXFTSgOy2EBClQTousGCUrqSUYbh+tE E5GK5FeM/UHg0sc7kdP+vZn0Rm4Ol56h5pLP9bvHfnb8BBi4JrBblhK1R VlRhXQa49Iuw/RFcutw3fjuwCAm8cwambwgVakZrTlRIPARB/30ZCAKtV m9HhcbW27v17lyBybL5usWM51WXTPTFLpFZ3XIJ9woAajNnSFAGGFFVDk raVa7odn9MzJJxcjHQs9Y6/aFnLVET8bmOMYtDGmbOyxpmfekM4D6IWG4 iTJFskpW4/OIo2R8zlD0dNfIoPHFlvI1ABr5yRfscQhC/83PdRvxIVPK+ g==; X-IronPort-AV: E=Sophos;i="5.60,418,1549900800"; d="scan'208";a="109007076" Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 02 May 2019 04:07:35 +0800 IronPort-SDR: tQrrRNvF4mB0eVKXoFSR7oq5/I+VgJyD2SNPqpfYRZOKSTq876EsnFYNxZf9WxLnCwrKUYyp4r 6ccpok1wVpeU0ltWoTMyb1qU+8Vn2q1L5gjtRJ7ppZDudkrifFFjXU+0ixswcLVHbC1T9b/ifu i0tqWaIB0kTwmzwLTelT/lV1V7BAToZN46FUxDdxGtt6v7VVhyXX6KFf39yOn3vgiVHivWBcJr T9/awXhf2SeMUKWVrGJ1NY2Xw5Zsl9ItLrNlBgzWjIfpt6tJPTAfzy+guBmKvLvLIC+lJXkbEK HoAjSRn/9HDOLIC4zeXPM0my Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep01.wdc.com with ESMTP; 01 May 2019 12:43:53 -0700 IronPort-SDR: YKYEFNVOoWeqh/VEAj3qtuR3KDRrLg/0lil/feSO/u4ekmZgeni03xQBFoPICKvVl3YBRXaVer iRddzOraEjllJ3PoMbmQckPBxbt4cvosBSPsbuuN0TANBykRbHLGIkDUwEgGpcKtLwV87GFGcl 8sEOIWGAeUHUTKsPIpQ3jBZQOm67+LM1rtEnFzFi7jWU+EhnJq5Ku7CGiRchw4cK+bpCfVEnr7 CPIlWNaMPy1KnbhcQ/vVwotzCcqzsCsQ3K3ejumWrpuYUb37pXUoxzKmMNcmvoGI/XwfV3W6KK il8= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip02.wdc.com with ESMTP; 01 May 2019 13:07:34 -0700 From: Atish Patra To: u-boot@lists.denx.de Date: Wed, 1 May 2019 13:07:31 -0700 Message-Id: <20190501200731.9858-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Cc: Michal Simek , Boris Brezillon , Joe Hershberger , Alexander Graf Subject: [U-Boot] [v3 PATCH] RISCV: image: Add booti support. X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds booti support for RISC-V Linux kernel. The existing bootm method will also continue to work as it is. It depends on the following kernel patch which adds the header to the flat Image. Gzip compressed Image (Image.gz) support is not enabled with this patch. https://patchwork.kernel.org/patch/10925543/ Tested on HiFive Unleashed and QEMU. Signed-off-by: Atish Patra Reviewed-by: Tom Rini Tested-by: Karsten Merker --- Changes from v2->v3 1. Updated the image header structure as per kernel patch. 2. Removed Image.gz support as it will be added as separate RFC patch. --- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/image.c | 55 +++++++++++++++++++++++++++++++++++++++++ cmd/Kconfig | 2 +- cmd/booti.c | 8 ++++-- 4 files changed, 63 insertions(+), 3 deletions(-) create mode 100644 arch/riscv/lib/image.c diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 1c332db436a9..6ae6ebbeafda 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -7,6 +7,7 @@ # Rick Chen, Andes Technology Corporation obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_RISCV_RDTIME) += rdtime.o diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c new file mode 100644 index 000000000000..d063beb7dfbe --- /dev/null +++ b/arch/riscv/lib/image.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Western Digital Corporation or its affiliates. + * Authors: + * Atish Patra + * Based on arm/lib/image.c + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* ASCII version of "RISCV" defined in Linux kernel */ +#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952 + +struct linux_image_h { + uint32_t code0; /* Executable code */ + uint32_t code1; /* Executable code */ + uint64_t text_offset; /* Image load offset */ + uint64_t image_size; /* Effective Image size */ + uint64_t res1; /* reserved */ + uint64_t res2; /* reserved */ + uint64_t res3; /* reserved */ + uint64_t magic; /* Magic number */ + uint32_t res4; /* reserved */ + uint32_t res5; /* reserved */ +}; + +int booti_setup(ulong image, ulong *relocated_addr, ulong *size, + bool force_reloc) +{ + struct linux_image_h *lhdr; + + lhdr = (struct linux_image_h *)map_sysmem(image, 0); + + if (lhdr->magic != LINUX_RISCV_IMAGE_MAGIC) { + puts("Bad Linux RISCV Image magic!\n"); + return -EINVAL; + } + + if (lhdr->image_size == 0) { + puts("Image lacks image_size field, error!\n"); + return -EINVAL; + } + *size = lhdr->image_size; + *relocated_addr = gd->ram_base + lhdr->text_offset; + + unmap_sysmem(lhdr); + + return 0; +} diff --git a/cmd/Kconfig b/cmd/Kconfig index 2bdbfcb3d091..d427b66d3714 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -212,7 +212,7 @@ config CMD_BOOTZ config CMD_BOOTI bool "booti" - depends on ARM64 + depends on ARM64 || RISCV default y help Boot an AArch64 Linux Kernel image from memory. diff --git a/cmd/booti.c b/cmd/booti.c index 04353b68eccc..c22ba9bae2e4 100644 --- a/cmd/booti.c +++ b/cmd/booti.c @@ -77,7 +77,11 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bootm_disable_interrupts(); images.os.os = IH_OS_LINUX; + #ifdef CONFIG_RISCV_SMODE + images.os.arch = IH_ARCH_RISCV; + #elif CONFIG_ARM64 images.os.arch = IH_ARCH_ARM64; + #endif ret = do_bootm_states(cmdtp, flag, argc, argv, #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH BOOTM_STATE_RAMDISK | @@ -92,7 +96,7 @@ int do_booti(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #ifdef CONFIG_SYS_LONGHELP static char booti_help_text[] = "[addr [initrd[:size]] [fdt]]\n" - " - boot arm64 Linux Image stored in memory\n" + " - boot arm64/riscv Linux Image stored in memory\n" "\tThe argument 'initrd' is optional and specifies the address\n" "\tof an initrd in memory. The optional parameter ':size' allows\n" "\tspecifying the size of a RAW initrd.\n" @@ -107,5 +111,5 @@ static char booti_help_text[] = U_BOOT_CMD( booti, CONFIG_SYS_MAXARGS, 1, do_booti, - "boot arm64 Linux Image image from memory", booti_help_text + "boot arm64/riscv Linux Image image from memory", booti_help_text );