From patchwork Thu Apr 11 02:56:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pierre Bourdon X-Patchwork-Id: 1083702 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="h5mDSPN+"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44fm0X27XCz9s3l for ; Thu, 11 Apr 2019 12:57:30 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 224B0C21E08; Thu, 11 Apr 2019 02:57:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E1F09C21C2F; Thu, 11 Apr 2019 02:57:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1FAB1C21C2F; Thu, 11 Apr 2019 02:57:24 +0000 (UTC) Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) by lists.denx.de (Postfix) with ESMTPS id 525AEC21BE5 for ; Thu, 11 Apr 2019 02:57:23 +0000 (UTC) Received: by mail-wm1-f68.google.com with SMTP id w15so4658969wmc.3 for ; Wed, 10 Apr 2019 19:57:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=lV/D1wKlqpnGh8R5j3voLK5LZPAYRzJM+exoJlqwnWM=; b=h5mDSPN+wyB/mVfp+Wzj9dQcurRcPT7XdR8DRIH5el4kABwAB62Jt604viAqhvZrf/ KGVSA54qSAnxb4UPVKVKlYbDil1VikbhHUkujZCZ1eFka+Tel+5gzYviCOhuLou+5aWg ej9x6RtKrIJRivuvvN+OC9765mEJo8J7Ore2Mnf7dsPEgY7PBpbdXNvcjddqruAq/rG/ FWIVJmDD26YS1GBbmnyYDRUQuLo6rwWun51KhL/+fm57epZC/M3/3qrHhl1ay1K+FooU D0fuAZiSowjgo8DDN3vn2+C11YMGPYEWPQK/SQnGjqAcMaXy3evJJuqVtk2g94E6j+nD zO1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=lV/D1wKlqpnGh8R5j3voLK5LZPAYRzJM+exoJlqwnWM=; b=lWJ6tcO4CDO6rpcc8pJHL3xBp/+qqokrw+mvoGFA0uxK5dl3fRWdJdm0edxitEnplx X4xkHru08QvC4oPw7gykoDYa1gf329JcNKHQDBHeApmzMHXa6E9p1MxnHcIevTjOr/m1 sE5Ze+bCp9NTpt/XqDwHH/hAjzCgwtjX2rxQ09h2L9haVDZEmbwfSnzk7lHc0rlOZScs BMJgpkafbekZ6f8swwLvv0gBS68bbwIjLBqqVx247Ea9PPcLddtdGwubuttuHe+ddS98 yfp5NAIkBd//dHht2L7Auj3sD1KXG+wvwk7BhzZV/2HU+cgV2weLcyLTZ8REa7ZIcvo2 cLsA== X-Gm-Message-State: APjAAAWVyiwMEmg/RLss23bntQl/Snc+eWvAhMjcP5cgksPOYWdBwaaA yf5qerbcCbG+s7qKAxnsAy0Xtp37FHU= X-Google-Smtp-Source: APXvYqx4M1TipkG2tpU5/0i3GBNzRb8tiKpRvW9/ZTsv6g1li484VD47hkKSWtkIR+Q2T31WggmaMQ== X-Received: by 2002:a1c:6783:: with SMTP id b125mr4713719wmc.79.1554951442430; Wed, 10 Apr 2019 19:57:22 -0700 (PDT) Received: from lowell.delroth.net ([2a02:168:6426::bb2]) by smtp.gmail.com with ESMTPSA id 4sm2990946wmg.12.2019.04.10.19.57.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Apr 2019 19:57:21 -0700 (PDT) From: Pierre Bourdon To: u-boot@lists.denx.de Date: Thu, 11 Apr 2019 04:56:58 +0200 Message-Id: <20190411025659.1780-1-delroth@gmail.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 Cc: Stefan Roese Subject: [U-Boot] [PATCH 1/2] mmc: mv_sdhci: add driver model support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The new DM implementation currently does not support the Sheeva 88SV331xV5 specific quirk present in the legacy implementation. The legacy code is thus kept for this SoC and others not yet migrated to DM_MMC. Signed-off-by: Pierre Bourdon Cc: Jaehoon Chung Cc: Stefan Roese Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/cpu.c | 2 +- arch/arm/mach-mvebu/include/mach/cpu.h | 2 + drivers/mmc/mv_sdhci.c | 67 +++++++++++++++++++++++++- 3 files changed, 69 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 919d05c88c..ced9b5480a 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -491,7 +491,7 @@ int arch_misc_init(void) } #endif /* CONFIG_ARCH_MISC_INIT */ -#ifdef CONFIG_MMC_SDHCI_MV +#if defined(CONFIG_MMC_SDHCI_MV) && !defined(CONFIG_DM_MMC) int board_mmc_init(bd_t *bis) { mv_sdh_init(MVEBU_SDIO_BASE, 0, 0, diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 9e23043a48..42456a8b33 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -141,7 +141,9 @@ u32 mvebu_get_nand_clock(void); void return_to_bootrom(void); +#ifndef CONFIG_DM_MMC int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks); +#endif void get_sar_freq(struct sar_freq_modes *sar_freq); diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index de4ae0a0e7..bf26d2e4e2 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -4,10 +4,13 @@ */ #include +#include #include #include #include +#define MVSDH_NAME "mv_sdh" + #define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4)) #define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4)) @@ -36,6 +39,8 @@ static void sdhci_mvebu_mbus_config(void __iomem *base) } } +#ifndef CONFIG_DM_MMC + #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS static struct sdhci_ops mv_ops; @@ -63,7 +68,6 @@ static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg) #endif /* CONFIG_SHEEVA_88SV331xV5 */ #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ -static char *MVSDH_NAME = "mv_sdh"; int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) { struct sdhci_host *host = NULL; @@ -90,3 +94,64 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) return add_sdhci(host, 0, min_clk); } + +#else + +DECLARE_GLOBAL_DATA_PTR; + +struct mv_sdhci_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +static int mv_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct mv_sdhci_plat *plat = dev_get_platdata(dev); + struct sdhci_host *host = dev_get_priv(dev); + int ret; + + host->name = MVSDH_NAME; + host->ioaddr = (void *)devfdt_get_addr(dev); + host->quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD; + + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); + if (ret) + return ret; + + if (CONFIG_IS_ENABLED(ARCH_MVEBU)) { + /* Configure SDHCI MBUS mbus bridge windows */ + sdhci_mvebu_mbus_config(host->ioaddr); + } + + host->mmc = &plat->mmc; + host->mmc->dev = dev; + host->mmc->priv = host; + upriv->mmc = host->mmc; + + return sdhci_probe(dev); +} + +static int mv_sdhci_bind(struct udevice *dev) +{ + struct mv_sdhci_plat *plat = dev_get_platdata(dev); + + return sdhci_bind(dev, &plat->mmc, &plat->cfg); +} + +static const struct udevice_id mv_sdhci_ids[] = { + { .compatible = "marvell,armada-380-sdhci" }, + { } +}; + +U_BOOT_DRIVER(mv_sdhci_drv) = { + .name = MVSDH_NAME, + .id = UCLASS_MMC, + .of_match = mv_sdhci_ids, + .bind = mv_sdhci_bind, + .probe = mv_sdhci_probe, + .ops = &sdhci_ops, + .priv_auto_alloc_size = sizeof(struct sdhci_host), + .platdata_auto_alloc_size = sizeof(struct mv_sdhci_plat), +}; +#endif /* CONFIG_DM_MMC */