From patchwork Thu Mar 7 08:27:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 1052719 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="nbgkB1jh"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44FP6z2fLrz9sD4 for ; Thu, 7 Mar 2019 19:34:03 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 16404C21DD7; Thu, 7 Mar 2019 08:30:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id ED95CC21DB6; Thu, 7 Mar 2019 08:29:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 93E11C21E34; Thu, 7 Mar 2019 08:28:43 +0000 (UTC) Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by lists.denx.de (Postfix) with ESMTPS id 606C1C21C2C for ; Thu, 7 Mar 2019 08:28:39 +0000 (UTC) Received: by mail-pf1-f196.google.com with SMTP id n125so10872426pfn.5 for ; Thu, 07 Mar 2019 00:28:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iR7iMlgvDd3lC69UTFphxCQOukHhwqlYvIIBtIfLiek=; b=nbgkB1jhUU1zfPsLTiET0lkLRqEtE/XlwWXXe6eHQj/R2aCfanIN1YrR+7KhXrBwvG g8mpDaYHPvvY6bMdEAk0R5WFp2nkSn9HbmZ/t26usKoW8Z/u7243lqMrKYhx/lzw4XUe KgotDLs053W3Y3RTZqyYuRlF27RvNaH6XNRQerdw/0di3NMbumlBOlJ1whp05D6GYT/c jrf2qsanGzgGhr+zI8NvMhLjjV+E89fEVfGLXgdnQIU6yCT3heLjrgzFFLEmtJRGJ/Tx uwHR1n5M+g6x7gU+8SCA8xTn6WF0MfrqzK/slP+4nRAbBCkRFEYNajj51vPPYzMkDFWB S8eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iR7iMlgvDd3lC69UTFphxCQOukHhwqlYvIIBtIfLiek=; b=Pm3dcDsqfeBS4uqHRUmXanph/fDjq/WqsHNNeAfPGFWyAA4mNjORSH2UGp7j0nQS4A z79O1OPt4lk7PAXKtuyz6vRWDgY+Ty4DwW0zohzAugiQZwi02VEshreSigC+EK+ADfSV 0/NrHm5Z/QuTDMsmM/ospcZxzfs7W82+ZQ9eAqzfnMI+DGB5a8vANI+vdlju98eSwb36 voatPqyQOC/t+bfbJzSPYk1UJJ1+S2G1h9nmvsZjN81X8Nm8J+YvTQpkYOYAZZCtPmsa i+MnTuBXfJ2TsR0kj/kvRNiQeoGC5MGTT0xiAdQg127ni336OoNOtgQiOFjys2oMiP9m UlUQ== X-Gm-Message-State: APjAAAVgxHrrmq7wV5VLlz+9TtMvmKPydbXLJmOhg+YpOMP3IcWTaJae +J53RTErN6F4+vKiiIHMvXOxMExFvBY= X-Google-Smtp-Source: APXvYqyHbHP7gLUmHUl6zTuQfYcsdwN9JGX4fJy480g1IuGf1i7M+JtolGAL8X7o0TJx7OLWwJuX6Q== X-Received: by 2002:a63:9246:: with SMTP id s6mr10180292pgn.349.1551947317637; Thu, 07 Mar 2019 00:28:37 -0800 (PST) Received: from chrisp-dl.ws.atlnz.lc ([2001:df5:b000:22:3a2c:4aff:fe70:2b02]) by smtp.gmail.com with ESMTPSA id 63sm7709227pfy.110.2019.03.07.00.28.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Mar 2019 00:28:37 -0800 (PST) From: Chris Packham To: u-boot@lists.denx.de Date: Thu, 7 Mar 2019 21:27:57 +1300 Message-Id: <20190307082805.15199-5-judge.packham@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190307082805.15199-1-judge.packham@gmail.com> References: <20190307082805.15199-1-judge.packham@gmail.com> MIME-Version: 1.0 Cc: Tom Rini , Prafulla Wadaskar , Luka Perkov , Stefan Roese , Chris Packham Subject: [U-Boot] [PATCH v2 04/12] ARM: kirkwood: switch to using mvebu mbus X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The mvebu mbus code already had most of the support required for kirkwood. The only difference is that unlike the other mvebu targets kirkwood doesn't have a bridge control block so the code related to managing that needs to be compiled out. Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- arch/arm/mach-kirkwood/cpu.c | 33 ++++++++++++++++++++--- arch/arm/mach-kirkwood/include/mach/cpu.h | 11 ++++++++ arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/mbus.c | 6 +++++ 4 files changed, 48 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 85c7f5903d94..311c5d50e2f9 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -110,6 +110,32 @@ int kw_config_adr_windows(void) return 0; } +static struct mbus_win windows[] = { + /* Window 0: PCIE MEM address space */ + { KW_DEFADR_PCI_MEM, 1024 * 1024 * 256, + KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_MEM }, + + /* Window 1: PCIE IO address space */ + { KW_DEFADR_PCI_IO, 1024 * 64, + KWCPU_TARGET_PCIE, KWCPU_ATTR_PCIE_IO }, + + /* Window 2: NAND Flash address space */ + { KW_DEFADR_NANDF, 1024 * 1024 * 128, + KWCPU_TARGET_MEMORY, KWCPU_ATTR_NANDFLASH }, + + /* Window 3: SPI Flash address space */ + { KW_DEFADR_SPIF, 1024 * 1024 * 128, + KWCPU_TARGET_MEMORY, KWCPU_ATTR_SPIFLASH }, + + /* Window 4: BOOT Memory address space */ + { KW_DEFADR_BOOTROM, 1024 * 1024 * 128, + KWCPU_TARGET_MEMORY, KWCPU_ATTR_BOOTROM }, + + /* Window 5: Security SRAM address space */ + { KW_DEFADR_SASRAM, 1024 * 64, + KWCPU_TARGET_SASRAM, KWCPU_ATTR_SASRAM }, +}; + /* * SYSRSTn Duration Counter Support * @@ -221,15 +247,13 @@ int arch_cpu_init(void) struct kwcpu_registers *cpureg = (struct kwcpu_registers *)KW_CPU_REG_BASE; - /* Linux expects` the internal registers to be at 0xf1000000 */ + /* Linux expects the internal registers to be at 0xf1000000 */ writel(KW_REGS_PHY_BASE, KW_OFFSET_REG); /* Enable and invalidate L2 cache in write through mode */ writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg); invalidate_l2_cache(); - kw_config_adr_windows(); - #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* * Configures the I/O voltage of the pads connected to Egigabit @@ -295,6 +319,9 @@ int arch_misc_init(void) temp = get_cr(); set_cr(temp & ~CR_V); + /* Configure mbus windows */ + mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); + /* checks and execute resset to factory event */ kw_sysrst_check(); diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h index c35cace844ae..3d6b15568a8a 100644 --- a/arch/arm/mach-kirkwood/include/mach/cpu.h +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -68,6 +68,13 @@ enum kwcpu_attrib { #define KW_DEFADR_SPIF 0xE8000000 #define KW_DEFADR_BOOTROM 0xF8000000 +struct mbus_win { + u32 base; + u32 size; + u8 target; + u8 attr; +}; + /* * read feroceon/sheeva core extra feature register * using co-proc instruction @@ -134,6 +141,9 @@ struct kwgpio_registers { u32 irq_level; }; +/* Needed for dynamic (board-specific) mbus configuration */ +extern struct mvebu_mbus_state mbus_state; + /* * functions */ @@ -141,6 +151,7 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank); unsigned int mvebu_sdram_bs(enum memory_bank bank); void mvebu_sdram_size_adjust(enum memory_bank bank); int kw_config_adr_windows(void); +int mvebu_mbus_probe(struct mbus_win windows[], int count); void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, unsigned int gpp0_oe, unsigned int gpp1_oe); int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index ee2eca913484..c0274a6f09aa 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -14,6 +14,7 @@ ifdef CONFIG_KIRKWOOD obj-y = dram.o obj-y += gpio.o +obj-y += mbus.o obj-y += timer.o else # CONFIG_KIRKWOOD diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index df4c5cb2d718..9b2c57348266 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -405,6 +405,7 @@ int mvebu_mbus_del_window(phys_addr_t base, size_t size) return 0; } +#ifndef CONFIG_KIRKWOOD static void mvebu_mbus_get_lowest_base(struct mvebu_mbus_state *mbus, phys_addr_t *base) { @@ -428,7 +429,9 @@ static void mvebu_mbus_get_lowest_base(struct mvebu_mbus_state *mbus, *base = wbase; } } +#endif +#ifndef CONFIG_KIRKWOOD static void mvebu_config_mbus_bridge(struct mvebu_mbus_state *mbus) { phys_addr_t base; @@ -451,6 +454,7 @@ static void mvebu_config_mbus_bridge(struct mvebu_mbus_state *mbus) val = (size / (64 << 10)) - 1; writel((val << 16) | 0x1, MBUS_BRIDGE_WIN_CTRL_REG); } +#endif int mbus_dt_setup_win(struct mvebu_mbus_state *mbus, u32 base, u32 size, u8 target, u8 attr) @@ -471,12 +475,14 @@ int mbus_dt_setup_win(struct mvebu_mbus_state *mbus, return -ENOMEM; } +#ifndef CONFIG_KIRKWOOD /* * Re-configure the mbus bridge registers each time this function * is called. Since it may get called from the board code in * later boot stages as well. */ mvebu_config_mbus_bridge(mbus); +#endif return 0; }