From patchwork Tue Mar 5 22:53:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 1052035 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44DXMj5vzTz9s1B for ; Wed, 6 Mar 2019 09:57:05 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6EAA7C21DF9; Tue, 5 Mar 2019 22:56:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AFF55C21E45; Tue, 5 Mar 2019 22:54:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id DA408C21DF8; Tue, 5 Mar 2019 22:54:42 +0000 (UTC) Received: from mail-edgeKA24.fraunhofer.de (mail-edgeka24.fraunhofer.de [153.96.1.24]) by lists.denx.de (Postfix) with ESMTPS id 003A4C21E02 for ; Tue, 5 Mar 2019 22:54:37 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2FuAACJ/X5c/xoBYJlkHAEBAQQBAQcEAQGBUwUBAQsBgg+BWTmNAYprmi6Bew2EbAKELSI2Bw0BAQMBAQMBAwICAmkohUwGMgFBBRBRPRoGDgWDIoF1AaxbijAJAYElAYZjhESBVz+BEAGIYIUUAolwIAGCCJduBwKBIoEaBJAoDBmKdYgynTKBTgsngVYzGiSDO5BMPgEyAZEUAQE X-IPAS-Result: A2FuAACJ/X5c/xoBYJlkHAEBAQQBAQcEAQGBUwUBAQsBgg+BWTmNAYprmi6Bew2EbAKELSI2Bw0BAQMBAQMBAwICAmkohUwGMgFBBRBRPRoGDgWDIoF1AaxbijAJAYElAYZjhESBVz+BEAGIYIUUAolwIAGCCJduBwKBIoEaBJAoDBmKdYgynTKBTgsngVYzGiSDO5BMPgEyAZEUAQE X-IronPort-AV: E=Sophos;i="5.58,445,1544482800"; d="scan'208";a="13621768" Received: from mail-mtaka26.fraunhofer.de ([153.96.1.26]) by mail-edgeKA24.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Mar 2019 23:54:38 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0BPAADM/H5c/xBhWMBkHAEBAQQBAQcEAQGBUwUBAQsBhCGNAaUZgXsNhGwChE42Bw0BAQMBAQMBAwJtKIVLBjIBQQUQUT0aBg4FgyKBdqxcijAJAYElAYZjhhs/gRABiGCFFAKJcCABggiXbgcCgSKBGgSQKAwZinWIMp0ygU4LJoFWMxokgzuQTD4DMAGRFAEB X-IronPort-AV: E=Sophos;i="5.58,445,1544482800"; d="scan'208";a="33777143" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP12EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA26.fraunhofer.de with ESMTP/TLS/AES256-SHA; 05 Mar 2019 23:54:37 +0100 Received: from localhost.de (10.80.233.51) by FGDEMUCIMP12EXC.ads.fraunhofer.de (10.80.232.43) with Microsoft SMTP Server (TLS) id 14.3.435.0; Tue, 5 Mar 2019 23:56:33 +0100 From: Lukas Auer To: Date: Tue, 5 Mar 2019 23:53:29 +0100 Message-ID: <20190305225331.1353-8-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190305225331.1353-1-lukas.auer@aisec.fraunhofer.de> References: <20190305225331.1353-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24472.002 X-TM-AS-Result: No--4.041000-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Palmer Dabbelt , Andreas Schwab , Alexander Graf Subject: [U-Boot] [PATCH v2 7/9] riscv: do not rely on hart ID passed by previous boot stage X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" RISC-V U-Boot expects the hart ID to be passed to it via register a0 by the previous boot stage. Machine mode firmware such as BBL and OpenSBI do this when starting their payload (U-Boot) in supervisor mode. If U-Boot is running in machine mode, this task must be handled by the boot ROM. Explicitly populate register a0 with the hart ID from the mhartid CSR to avoid possible problems on RISC-V processors with a boot ROM that does not handle this task. Suggested-by: Rick Chen Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Rick Chen Tested-by: Rick Chen --- Changes in v2: - New patch to populate register a0 with the hart ID from the mhartid CSR in machine-mode arch/riscv/cpu/start.S | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 79b753847c..d4daa6e0bf 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -36,6 +36,10 @@ .section .text .globl _start _start: +#ifdef CONFIG_RISCV_MMODE + csrr a0, mhartid +#endif + /* save hart id and dtb pointer */ mv s0, a0 mv s1, a1