From patchwork Tue Mar 5 22:53:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 1052039 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44DXPN4BwVz9s1B for ; Wed, 6 Mar 2019 09:58:32 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 11094C21E35; Tue, 5 Mar 2019 22:55:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 70730C21E3E; Tue, 5 Mar 2019 22:54:46 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B6228C21DDC; Tue, 5 Mar 2019 22:54:36 +0000 (UTC) Received: from mail-edgeKA24.fraunhofer.de (mail-edgeka24.fraunhofer.de [153.96.1.24]) by lists.denx.de (Postfix) with ESMTPS id B309BC21DD9 for ; Tue, 5 Mar 2019 22:54:32 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2EQAACJ/X5c/xoBYJlkGwEBAQEDAQEBBwMBAQGBUQYBAQELAYIPgVk5jCJfimuLO45zFIFnDYRsAoQtIjQJDQEBAwEBAwEDAgICaRwMhUwGMgFGEFEhHBoGDgWDIoFeAxQBrFuIBQ2CHgkBgSUBhmOERIFXP4EQAYVpgW8kZIUUAowZlzszBwKBIoEaBIx3gzEMGYp1iDKRb4tDgUc5gVYzGiSDO4Vxils+ATIBkRQBAQ X-IPAS-Result: A2EQAACJ/X5c/xoBYJlkGwEBAQEDAQEBBwMBAQGBUQYBAQELAYIPgVk5jCJfimuLO45zFIFnDYRsAoQtIjQJDQEBAwEBAwEDAgICaRwMhUwGMgFGEFEhHBoGDgWDIoFeAxQBrFuIBQ2CHgkBgSUBhmOERIFXP4EQAYVpgW8kZIUUAowZlzszBwKBIoEaBIx3gzEMGYp1iDKRb4tDgUc5gVYzGiSDO4Vxils+ATIBkRQBAQ X-IronPort-AV: E=Sophos;i="5.58,445,1544482800"; d="scan'208";a="13621763" Received: from mail-mtaka26.fraunhofer.de ([153.96.1.26]) by mail-edgeKA24.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Mar 2019 23:54:33 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0AlAADM/H5c/xBhWMBkHAEBAQQBAQcEAQGBUQcBAQsBhCGMIl+WJo5zFIFnDYRsAoRONAkNAQEDAQEDAQMCbRwMhUsGMgFGEFEhHBoGDgWDIoFeAxWsXIgFDYIeCQGBJQGGY4YbP4EQAYVpgW8kZIUUAowZlzszBwKBIoEaBIx3gzEMGYp1iDKRb4tDgUc4gVYzGiSDO4Vxils+AzABkRQBAQ X-IronPort-AV: E=Sophos;i="5.58,445,1544482800"; d="scan'208";a="33777135" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP12EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA26.fraunhofer.de with ESMTP/TLS/AES256-SHA; 05 Mar 2019 23:54:32 +0100 Received: from localhost.de (10.80.233.51) by FGDEMUCIMP12EXC.ads.fraunhofer.de (10.80.232.43) with Microsoft SMTP Server (TLS) id 14.3.435.0; Tue, 5 Mar 2019 23:56:27 +0100 From: Lukas Auer To: Date: Tue, 5 Mar 2019 23:53:25 +0100 Message-ID: <20190305225331.1353-4-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190305225331.1353-1-lukas.auer@aisec.fraunhofer.de> References: <20190305225331.1353-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24472.002 X-TM-AS-Result: No--1.996000-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Palmer Dabbelt , Andreas Schwab , Alexander Graf Subject: [U-Boot] [PATCH v2 3/9] riscv: implement IPI platform functions using SBI X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Atish Patra Tested-by: Bin Meng --- Changes in v2: None arch/riscv/Kconfig | 5 +++++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/sbi_ipi.c | 25 +++++++++++++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 arch/riscv/lib/sbi_ipi.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4d7a115569..9da609b33b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -139,4 +139,9 @@ config NR_CPUS Stack memory is pre-allocated. U-Boot must therefore know the maximum number of CPUs that may be present. +config SBI_IPI + bool + default y if RISCV_SMODE + depends on SMP + endmenu diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 19370f9749..35dbf643e4 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_RISCV_RDTIME) += rdtime.o obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-y += interrupts.o obj-y += reset.o +obj-$(CONFIG_SBI_IPI) += sbi_ipi.o obj-y += setjmp.o obj-$(CONFIG_SMP) += smp.o diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c new file mode 100644 index 0000000000..170346da68 --- /dev/null +++ b/arch/riscv/lib/sbi_ipi.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Fraunhofer AISEC, + * Lukas Auer + */ + +#include +#include + +int riscv_send_ipi(int hart) +{ + ulong mask; + + mask = 1UL << hart; + sbi_send_ipi(&mask); + + return 0; +} + +int riscv_clear_ipi(int hart) +{ + sbi_clear_ipi(); + + return 0; +}