Message ID | 20190305225331.1353-4-lukas.auer@aisec.fraunhofer.de |
---|---|
State | Superseded |
Delegated to: | Andes |
Headers | show |
Series | SMP support for RISC-V | expand |
On 3/5/19 2:54 PM, Lukas Auer wrote: > The supervisor binary interface (SBI) provides the necessary functions > to implement the platform IPI functions riscv_send_ipi() and > riscv_clear_ipi(). Use it to implement them. > > This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs > running in supervisor mode. Support for machine mode is already > available for CPUs that include the SiFive CLINT. > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > Reviewed-by: Anup Patel <anup.patel@wdc.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > --- > > Changes in v2: None > > arch/riscv/Kconfig | 5 +++++ > arch/riscv/lib/Makefile | 1 + > arch/riscv/lib/sbi_ipi.c | 25 +++++++++++++++++++++++++ > 3 files changed, 31 insertions(+) > create mode 100644 arch/riscv/lib/sbi_ipi.c > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 4d7a115569..9da609b33b 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -139,4 +139,9 @@ config NR_CPUS > Stack memory is pre-allocated. U-Boot must therefore know the > maximum number of CPUs that may be present. > > +config SBI_IPI > + bool > + default y if RISCV_SMODE > + depends on SMP > + > endmenu > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile > index 19370f9749..35dbf643e4 100644 > --- a/arch/riscv/lib/Makefile > +++ b/arch/riscv/lib/Makefile > @@ -13,6 +13,7 @@ obj-$(CONFIG_RISCV_RDTIME) += rdtime.o > obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o > obj-y += interrupts.o > obj-y += reset.o > +obj-$(CONFIG_SBI_IPI) += sbi_ipi.o > obj-y += setjmp.o > obj-$(CONFIG_SMP) += smp.o > > diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c > new file mode 100644 > index 0000000000..170346da68 > --- /dev/null > +++ b/arch/riscv/lib/sbi_ipi.c > @@ -0,0 +1,25 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2019 Fraunhofer AISEC, > + * Lukas Auer <lukas.auer@aisec.fraunhofer.de> > + */ > + > +#include <common.h> > +#include <asm/sbi.h> > + > +int riscv_send_ipi(int hart) > +{ > + ulong mask; > + > + mask = 1UL << hart; > + sbi_send_ipi(&mask); > + > + return 0; > +} > + > +int riscv_clear_ipi(int hart) > +{ > + sbi_clear_ipi(); > + > + return 0; > +} > LGTM. Reviewed-by: Atish Patra <atish.patra@wdc.com> Regards, Atish
On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer <lukas.auer@aisec.fraunhofer.de> wrote: > > The supervisor binary interface (SBI) provides the necessary functions > to implement the platform IPI functions riscv_send_ipi() and > riscv_clear_ipi(). Use it to implement them. > > This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs > running in supervisor mode. Support for machine mode is already > available for CPUs that include the SiFive CLINT. > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> > Reviewed-by: Anup Patel <anup.patel@wdc.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > --- > > Changes in v2: None > > arch/riscv/Kconfig | 5 +++++ > arch/riscv/lib/Makefile | 1 + > arch/riscv/lib/sbi_ipi.c | 25 +++++++++++++++++++++++++ > 3 files changed, 31 insertions(+) > create mode 100644 arch/riscv/lib/sbi_ipi.c > Tested-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 4d7a115569..9da609b33b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -139,4 +139,9 @@ config NR_CPUS Stack memory is pre-allocated. U-Boot must therefore know the maximum number of CPUs that may be present. +config SBI_IPI + bool + default y if RISCV_SMODE + depends on SMP + endmenu diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 19370f9749..35dbf643e4 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_RISCV_RDTIME) += rdtime.o obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-y += interrupts.o obj-y += reset.o +obj-$(CONFIG_SBI_IPI) += sbi_ipi.o obj-y += setjmp.o obj-$(CONFIG_SMP) += smp.o diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c new file mode 100644 index 0000000000..170346da68 --- /dev/null +++ b/arch/riscv/lib/sbi_ipi.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Fraunhofer AISEC, + * Lukas Auer <lukas.auer@aisec.fraunhofer.de> + */ + +#include <common.h> +#include <asm/sbi.h> + +int riscv_send_ipi(int hart) +{ + ulong mask; + + mask = 1UL << hart; + sbi_send_ipi(&mask); + + return 0; +} + +int riscv_clear_ipi(int hart) +{ + sbi_clear_ipi(); + + return 0; +}