[U-Boot,v2,9/9] riscv: qemu: enable SMP

Message ID	20190305225331.1353-10-lukas.auer@aisec.fraunhofer.de
State	Superseded
Delegated to:	Andes
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Lukas Auer <lukas.auer@aisec.fraunhofer.de> To: <u-boot@lists.denx.de> Date: Tue, 5 Mar 2019 23:53:31 +0100 Message-ID: <20190305225331.1353-10-lukas.auer@aisec.fraunhofer.de> In-Reply-To: <20190305225331.1353-1-lukas.auer@aisec.fraunhofer.de> References: <20190305225331.1353-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 Cc: Palmer Dabbelt <palmer@sifive.com>, Andreas Schwab <schwab@suse.de>, Alexander Graf <agraf@suse.de> Subject: [U-Boot] [PATCH v2 9/9] riscv: qemu: enable SMP Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	SMP support for RISC-V \| expand [U-Boot,v2,0/9] SMP support for RISC-V [U-Boot,v2,1/9] riscv: add infrastructure for calling functions on other harts [U-Boot,v2,2/9] riscv: import the supervisor binary interface header file [U-Boot,v2,3/9] riscv: implement IPI platform functions using SBI [U-Boot,v2,4/9] riscv: delay initialization of caches and debug UART [U-Boot,v2,5/9] riscv: add support for multi-hart systems [U-Boot,v2,6/9] riscv: boot images passed to bootm on all harts [U-Boot,v2,7/9] riscv: do not rely on hart ID passed by previous boot stage [U-Boot,v2,8/9] riscv: fu540: enable SMP [U-Boot,v2,9/9] riscv: qemu: enable SMP

Message ID

20190305225331.1353-10-lukas.auer@aisec.fraunhofer.de

State

Superseded

Delegated to:

Andes

Headers

From: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
To: <u-boot@lists.denx.de>
Date: Tue, 5 Mar 2019 23:53:31 +0100
Message-ID: <20190305225331.1353-10-lukas.auer@aisec.fraunhofer.de>
In-Reply-To: <20190305225331.1353-1-lukas.auer@aisec.fraunhofer.de>
References: <20190305225331.1353-1-lukas.auer@aisec.fraunhofer.de>
MIME-Version: 1.0
Cc: Palmer Dabbelt <palmer@sifive.com>, Andreas Schwab <schwab@suse.de>,
	Alexander Graf <agraf@suse.de>
Subject: [U-Boot] [PATCH v2 9/9] riscv: qemu: enable SMP
Precedence: list
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: base64
Errors-To: u-boot-bounces@lists.denx.de
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

SMP support for RISC-V | expand

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> --- Changes in v2: None board/emulation/qemu-riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)

Comments

Bin Meng March 10, 2019, 1:01 p.m. UTC | #1

On Wed, Mar 6, 2019 at 6:54 AM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> Reviewed-by: Anup Patel <anup.patel@wdc.com>
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
> Changes in v2: None
>
>  board/emulation/qemu-riscv/Kconfig | 1 +
>  1 file changed, 1 insertion(+)
>

Tested-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 88d07d568e..cf057e7de6 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -34,5 +34,6 @@  config BOARD_SPECIFIC_OPTIONS # dummy
 	imply BOARD_LATE_INIT
 	imply OF_BOARD_SETUP
 	imply SIFIVE_SERIAL
+	imply SMP
 
 endif

[U-Boot,v2,9/9] riscv: qemu: enable SMP

Commit Message

Comments

Patch