From patchwork Mon Feb 25 08:15:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1047624 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="ToCasFqu"; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=sharedspace.onmicrosoft.com header.i=@sharedspace.onmicrosoft.com header.b="HN6NmIx4"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 447FJk3J7cz9s9T for ; Mon, 25 Feb 2019 19:21:10 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id EA1E4C21D8A; Mon, 25 Feb 2019 08:20:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=BAD_ENC_HEADER, KHOP_BIG_TO_CC, RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BE1CEC21DFA; Mon, 25 Feb 2019 08:15:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CA8ADC21DFA; Mon, 25 Feb 2019 08:15:23 +0000 (UTC) Received: from esa4.hgst.iphmx.com (esa4.hgst.iphmx.com [216.71.154.42]) by lists.denx.de (Postfix) with ESMTPS id CF29CC21E1B for ; Mon, 25 Feb 2019 08:15:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1551082517; x=1582618517; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=pCoXCPBfXT/wk3+fQHbpZdi5CTiQxXUuIcxCPAIOFSo=; b=ToCasFquCx//GlIJ/qs3Vg9idZvtWVz12n16/l4XgmZsIMF4Gfmpe35u EMqFGy/maMICmT0nivOGwiKAWhwX44BF9jx8JbOaqs7d9Y2ASLHnKBa+1 gY7VTOyvs1Yy6C3KQtMtQTeixKcpRwwe2WDa+bXLdUhI7KSrt5OR39xqQ r/objd4l60WwP+PMNCBJaRPqYs3QvMO6wKGG9rSTkRj1ver2tIJDZkxOO A3SlAEYWCPymTuRolR0YPBhVvC+mMY/Kdq49iyoXS7rHDpYJH/QxR9GbN 4FT3LrByzhZPvZLuQ5nZqR13ebxFqrGmzDc/tEtJdosqTfXXp30Tyq93J w==; X-IronPort-AV: E=Sophos;i="5.58,410,1544457600"; d="scan'208";a="102080796" Received: from mail-dm3nam03lp2056.outbound.protection.outlook.com (HELO NAM03-DM3-obe.outbound.protection.outlook.com) ([104.47.41.56]) by ob1.hgst.iphmx.com with ESMTP; 25 Feb 2019 16:15:15 +0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sharedspace.onmicrosoft.com; s=selector1-wdc-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZZB34B/CzEhFRK9+VzMubQrgwTt3jeoeLouxhZhH8Y0=; b=HN6NmIx4XGcM1K8XB4K6x3KEQw9uGWkBM2c9x3Au9BPz5fObr1cY5zf1ZolCKVR9lzbsYP4OnPRp5BPUnztiHwJuC+PjxvxQhGRNimZwVSijvVKxGvPBt1DIHiEJuUH3xmgWVFEtkKec9Fxjs2HgsJcC99c6SN+U696TN9AXwyk= Received: from MN2PR04MB6061.namprd04.prod.outlook.com (20.178.246.15) by MN2PR04MB5789.namprd04.prod.outlook.com (20.179.20.159) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1643.15; Mon, 25 Feb 2019 08:15:14 +0000 Received: from MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::d197:7b59:7e0d:e819]) by MN2PR04MB6061.namprd04.prod.outlook.com ([fe80::d197:7b59:7e0d:e819%3]) with mapi id 15.20.1643.019; Mon, 25 Feb 2019 08:15:14 +0000 From: Anup Patel To: Rick Chen , Bin Meng , Joe Hershberger , Michal Simek , Michal Simek , Lukas Auer , Masahiro Yamada , Simon Glass Thread-Topic: [PATCH v10 12/15] cpu: Bind timer driver for boot hart Thread-Index: AQHUzOI77+yrV1BGHUuM+AcS4dxslw== Date: Mon, 25 Feb 2019 08:15:14 +0000 Message-ID: <20190225081334.23256-13-anup.patel@wdc.com> References: <20190225081334.23256-1-anup.patel@wdc.com> In-Reply-To: <20190225081334.23256-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: TYAPR01CA0069.jpnprd01.prod.outlook.com (2603:1096:404:2b::33) To MN2PR04MB6061.namprd04.prod.outlook.com (2603:10b6:208:d8::15) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [129.253.179.161] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: e265744e-e1d5-4500-c5a0-08d69af95e2f x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(5600110)(711020)(4605104)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:MN2PR04MB5789; x-ms-traffictypediagnostic: MN2PR04MB5789: wdcipoutbound: EOP-TRUE x-microsoft-exchange-diagnostics: =?iso-8859-1?Q?1; MN2PR04MB5789; 23:FRIXbnl3kB/oWdbuGgE309lqkuUJXedFfZPZs+U?= =?iso-8859-1?q?rceWB16e3X/sHWae7kT8Ju/z/?= =?iso-8859-1?q?u8hJY1Qyak0i3asF3NJVjxt42M9RyDc8GXNa0QII6GPH1fgY5Iw?= =?iso-8859-1?q?zofHIkLYE7qXahKSggtKAoLVd8p90vjVDxDqUknnWQJxBCfa/KZ?= =?iso-8859-1?q?FK72jGQLvipInUyXEywcjP3T3lWZJjC6sD96So0gtKGyWc3OVa7?= =?iso-8859-1?q?+Ws/opl/rJKW3WYJ3YNIVJy7zxq328PMbTJ54fF8yZKYtIIFsWa?= =?iso-8859-1?q?99HoO+LLYsSGh1P5M5J8T/7QQqJEtGsupOo4mTLErfD/AR4WT2z?= =?iso-8859-1?q?M+5If7h4ldjJwU/3+AoVSPyWo3oclJnBcd/zetq3GfwizIue+rB?= =?iso-8859-1?q?vrTt5vmZF2BDcbsCOIy6PlleB15IFaNp77/39y4XhDEwt6p44a2?= =?iso-8859-1?q?Yjm8VqiP2GFlQ4lpy9KJj1+fxDMhTDoW5e5Z4830EkB+iCoa9ti?= =?iso-8859-1?q?r4waROo7Q5h2x0TFTV6Meh4sYt25wgb39zWOok1Gtp7OvOciufb?= =?iso-8859-1?q?f87VNZCxBVyG6UX5H2j9HxIhesR37zMiUOpD6J3ElZtcxxVIXkx?= =?iso-8859-1?q?+6v0BO0P365g3Q/z+O/dMs2kUVASIciJLlOBmJ6n2wPP7XAw4Vp?= =?iso-8859-1?q?BVpDhdpHHp6m5+tQlJM5OKWpLyPHI2ORH6k034snKuxpWH7zZJw?= =?iso-8859-1?q?R7HtQlOPLej0YkZGOJcWy4qSmkCdypkcj7MyD49JolcRIEc0EbG?= =?iso-8859-1?q?hcAxQ1Lzou82PVQ9WDlbPcQdWwHuGKoNRvyBHY63yfcYCQpAOP4?= =?iso-8859-1?q?GWQfT3XqFO6IPhXYdELAaGSpZ+e8puYe8faFIk2kkkrTLUqi0wy?= =?iso-8859-1?q?x4cos4Rt83WLmaFjEnHUnWzkK/WmdX5nZRIvMYSStbVQnrvML41?= =?iso-8859-1?q?Sh1JgNkq1lG414lk44h+P3oB7pj88DKFrKJfzkNBEpHk/vzjUSV?= =?iso-8859-1?q?4MUY5+ozS5/Y+xTZfLfBS4V9zuM+NHPCBfsaig4jGTpv1iURxYj?= =?iso-8859-1?q?NNxmUx1TtiFpPfnwduzlOSA8t3sHl5H7xNg+JggQzSbabhDqwjN?= =?iso-8859-1?q?hmxT1BOQgVOzaNk+9Yqs2fkKV+gMnC+YtJP9XZXbhE0mcx3aw8m?= =?iso-8859-1?q?3bgYcvDDcCdAzPJW7nSMFIb81pOM94x+lktFLnDQuSqIoU50nTd?= =?iso-8859-1?q?g7fbLN7h2XeNE4A0e0qfWSQybafXPVrpqMhXuxj9fudsFPrS0lv?= =?iso-8859-1?q?1M4i5cUcbLMVuNOafTjcFSWp4me13Eteumb3KG+vEzPlsw9eKCL?= =?iso-8859-1?q?xq7tqI698S4WBYDNi4nJR27NTzSiPiN06gf45kA9amMUfEA0EbH?= =?iso-8859-1?q?KtyxEe/b8s0x+w=3D=3D?= x-microsoft-antispam-prvs: x-forefront-prvs: 095972DF2F x-forefront-antispam-report: SFV:NSPM; SFS:(10019020)(376002)(346002)(396003)(366004)(39860400002)(136003)(189003)(199004)(66066001)(6512007)(186003)(53936002)(7736002)(305945005)(44832011)(478600001)(106356001)(26005)(486006)(2616005)(476003)(105586002)(7416002)(5660300002)(14454004)(6506007)(386003)(72206003)(8676002)(86362001)(54906003)(110136005)(81156014)(71190400001)(316002)(102836004)(6346003)(71200400001)(81166006)(1076003)(36756003)(25786009)(99286004)(97736004)(52116002)(50226002)(76176011)(2906002)(8936002)(11346002)(6486002)(6436002)(4326008)(68736007)(446003)(256004)(6116002)(3846002); DIR:OUT; SFP:1102; SCL:1; SRVR:MN2PR04MB5789; H:MN2PR04MB6061.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: PQHm0IHnlvoQ5nexvjRjIzMPLaZpCFOfn0NITCvds1vEKURpRwA/dTa2M8LzfkIgeobr4bqcGInCyv0pWm4/RLHx1KnTipxxvbxonjq43AATKlMFRotiey3ZD/u9a/EInGXJav+rhS4R/qptOwu6Etbh2w3kFnkRQuKXdmNjRxlEDzBs5Ey6d48BYujPrnKdpZB5wgJeFZ759xzSjUYX52C9/wpEeajODyfAMbAnMzBqU/1gXoblJNN9B63HXjSaNPcPyOrqyUJaCOo7zvUgQVmBDp7Ux3NsHTsQ5/Cc3V9EfhHFQxbyXy+praZrcTf5YsdQv0xRROLMP11fH/I3ZVk2thHnIGVMXgoQdFQOTBN3UEdH65UvzE7SvrF7TNAaSRKR3Cssx1ZNelqD5lFDaGwFmB2d/2pz70XN2aWF+LA= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: e265744e-e1d5-4500-c5a0-08d69af95e2f X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Feb 2019 08:15:09.2795 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB5789 Cc: Palmer Dabbelt , Alexander Graf , U-Boot Mailing List Subject: [U-Boot] [PATCH v10 12/15] cpu: Bind timer driver for boot hart X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Atish Patra Currently, timer driver is bound only for hart0. There is no mandatory requirement that hart0 should always come up. In fact, HiFive Unleashed SoC hart0 doesn't boot in S-mode because it only has M-mode. The timer driver should be bound for boot hart. Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Alexander Graf Reviewed-by: Lukas Auer Reviewed-by: Bin Meng --- drivers/cpu/riscv_cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 5e15df590e..f77c126499 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -10,6 +10,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size) { const char *isa; @@ -62,7 +64,6 @@ static int riscv_cpu_bind(struct udevice *dev) /* save the hart id */ plat->cpu_id = dev_read_addr(dev); - /* first examine the property in current cpu node */ ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); /* if not found, then look at the parent /cpus node */ @@ -71,7 +72,7 @@ static int riscv_cpu_bind(struct udevice *dev) &plat->timebase_freq); /* - * Bind riscv-timer driver on hart 0 + * Bind riscv-timer driver on boot hart. * * We only instantiate one timer device which is enough for U-Boot. * Pass the "timebase-frequency" value as the driver data for the @@ -80,7 +81,7 @@ static int riscv_cpu_bind(struct udevice *dev) * Return value is not checked since it's possible that the timer * driver is not included. */ - if (!plat->cpu_id && plat->timebase_freq) { + if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) { drv = lists_driver_lookup_name("riscv_timer"); if (!drv) { debug("Cannot find the timer driver, not included?\n");