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Thu, 21 Feb 2019 04:31:24 +0000 Received: from BN8PR04MB6050.namprd04.prod.outlook.com ([fe80::f87a:cb97:e3a:b8e7]) by BN8PR04MB6050.namprd04.prod.outlook.com ([fe80::f87a:cb97:e3a:b8e7%4]) with mapi id 15.20.1622.020; Thu, 21 Feb 2019 04:31:24 +0000 From: Anup Patel To: Rick Chen , Bin Meng , Joe Hershberger , Michal Simek , Michal Simek , Lukas Auer , Masahiro Yamada , Simon Glass Thread-Topic: [PATCH v9 12/15] cpu: Bind timer driver for boot hart Thread-Index: AQHUyZ5NOebUMGwjD0anbXp/1N7uhg== Date: Thu, 21 Feb 2019 04:31:24 +0000 Message-ID: <20190221042936.13441-13-anup.patel@wdc.com> References: <20190221042936.13441-1-anup.patel@wdc.com> In-Reply-To: <20190221042936.13441-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MAXPR0101CA0070.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:e::32) To BN8PR04MB6050.namprd04.prod.outlook.com (2603:10b6:408:53::32) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; 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There is no mandatory requirement that hart0 should always come up. In fact, HiFive Unleashed SoC hart0 doesn't boot in S-mode because it only has M-mode. The timer driver should be bound for boot hart. Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Alexander Graf Reviewed-by: Lukas Auer Reviewed-by: Bin Meng --- drivers/cpu/riscv_cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 5e15df590e..f77c126499 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -10,6 +10,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size) { const char *isa; @@ -62,7 +64,6 @@ static int riscv_cpu_bind(struct udevice *dev) /* save the hart id */ plat->cpu_id = dev_read_addr(dev); - /* first examine the property in current cpu node */ ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); /* if not found, then look at the parent /cpus node */ @@ -71,7 +72,7 @@ static int riscv_cpu_bind(struct udevice *dev) &plat->timebase_freq); /* - * Bind riscv-timer driver on hart 0 + * Bind riscv-timer driver on boot hart. * * We only instantiate one timer device which is enough for U-Boot. * Pass the "timebase-frequency" value as the driver data for the @@ -80,7 +81,7 @@ static int riscv_cpu_bind(struct udevice *dev) * Return value is not checked since it's possible that the timer * driver is not included. */ - if (!plat->cpu_id && plat->timebase_freq) { + if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) { drv = lists_driver_lookup_name("riscv_timer"); if (!drv) { debug("Cannot find the timer driver, not included?\n");