From patchwork Fri Feb 15 22:48:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Packham X-Patchwork-Id: 1043260 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cj6WPSfQ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 441T8l0dxRz9sMl for ; Sat, 16 Feb 2019 09:54:10 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 57385C21FFB; Fri, 15 Feb 2019 22:54:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 81BC2C22075; Fri, 15 Feb 2019 22:49:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 7375CC2204D; Fri, 15 Feb 2019 22:49:55 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id 810E1C22047 for ; Fri, 15 Feb 2019 22:49:28 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id e5so5644082plb.5 for ; Fri, 15 Feb 2019 14:49:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Fu8WW0TM0GGu0qfYBMBTneBDu9iukQHBGLwYVbAB/1I=; b=cj6WPSfQVa+7MJg50WbRtg9Odqg65xj3YtJvpZ7zy9CYB4r4Su7G3cZ/3GBzM6pMc1 SZuIbtZBl8XECUQU2dCacT4LuyxxHwm6BqaNx2ReS3dssF5YSNWlPswdjY4ooggzVBEC 8hkrgG9IgVkq4W7jpGrL1a+pxoHBrEcr9dxelBfUzZJ1IMjtp3llJiGQAuGtnqeHrr5h EfzpLV52UtoNoKWi1uDeLS7N/0Q9+4tk7ANY7gbj0FIoTIxyOUD1JRMJv7nIOuJrz5J3 m6x4Fa+nASssDFGgO2FvGYaDvuOD2pou2cC08BJyB/4XtE2ofADstwhaiRFl4osCO+HM 4cTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Fu8WW0TM0GGu0qfYBMBTneBDu9iukQHBGLwYVbAB/1I=; b=OhcfskO7Qb8jO7jtNZE1IRjc6fjJGfnmAIXOipDopbUZ+RcFSSJ3NfrwtYGNj9Hdit rea+6wpkxT3BlzOkFzIF7QGfjn0GHq6lBgpzPp0gUH9S7qMSyQ7kisaIswm4jOiJGy5l 4Si4t2kZxIH5OUICklsLOT1fq30WNrIX/O6RqmjBcpURjnjPTDpiInVcSkZtHXXDHhCL rOrsIJELvr9ZeJ0GheyJqqEyp+PCsgfjm9syaDdoyP6/YIcYPfL7Gn4TvHgEaIfsC+Iy abn5TFCzY9ciNqdOOvCUK0Ha2VkPxXa6IFv5DdQDBCD8vPPrUXOFNM0+l89joBQqhEpy CtjQ== X-Gm-Message-State: AHQUAubheN51rZb4G5iK2UexHC6fVAKLyskvbE3BQo7CFrXD7iFxcy3J sWU8nz6FycS6qAzLcKad5kmVyTrdg9sA2Q== X-Google-Smtp-Source: AHgI3IaeORETWKEHhsD+ir1n2qyRNosntCzD47UVAetDpZtLb5Wk3W+SDn3KWbFl7453mAal7XPi1g== X-Received: by 2002:a17:902:8d8d:: with SMTP id v13mr12365078plo.121.1550270966623; Fri, 15 Feb 2019 14:49:26 -0800 (PST) Received: from chrisp-dl.ws.atlnz.lc ([2001:df5:b000:22:3a2c:4aff:fe70:2b02]) by smtp.gmail.com with ESMTPSA id o85sm15523468pfi.105.2019.02.15.14.49.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 15 Feb 2019 14:49:26 -0800 (PST) From: Chris Packham To: u-boot@lists.denx.de Date: Sat, 16 Feb 2019 11:48:59 +1300 Message-Id: <20190215224902.28351-3-judge.packham@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190215224902.28351-1-judge.packham@gmail.com> References: <20190215224902.28351-1-judge.packham@gmail.com> MIME-Version: 1.0 Cc: Tom Rini , Baruch Siach , Prafulla Wadaskar , Luka Perkov , Joe Hershberger , Stefan Roese , Chris Packham Subject: [U-Boot] [PATCH v2 2/5] arm: mvebu: Add Marvell's integrated CPUs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Marvell's switch chips with integrated CPUs (collectively referred to as MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks (e.g. xor) are located at different addresses and DFX server exists as a separate target on the MBUS (on Armada-38x it's just part of the core complex registers). Signed-off-by: Chris Packham Reviewed-by: Stefan Roese --- Changes in v2: - use CONFIG_ARMADA_MSYS instead of just CONFIG_MSYS - Disable MBUS Error proagation arch/arm/mach-mvebu/Kconfig | 18 ++++++++++++- arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/cpu.c | 31 +++++++++++++++++++++-- arch/arm/mach-mvebu/include/mach/config.h | 2 +- arch/arm/mach-mvebu/include/mach/cpu.h | 3 +++ arch/arm/mach-mvebu/include/mach/soc.h | 20 +++++++++++++++ arch/arm/mach-mvebu/mbus.c | 5 ++++ drivers/ddr/marvell/axp/xor_regs.h | 4 +++ 8 files changed, 80 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 7dda04e0e34e..08c9972f02d7 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -46,7 +46,7 @@ config ARMADA_8K # Armada PLL frequency (used for NAND clock generation) config SYS_MVEBU_PLL_CLOCK int - default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K + default "2000000000" if ARMADA_XP || ARMADA_3700 || ARMADA_8K || ARMADA_MSYS default "1000000000" if ARMADA_38X || ARMADA_375 # Armada XP/38x SoC types... @@ -63,6 +63,22 @@ config MV78460 bool select ARMADA_XP +config ARMADA_MSYS + bool + select ARMADA_32BIT + +config 98DX4251 + bool + select ARMADA_MSYS + +config 98DX3336 + bool + select ARMADA_MSYS + +config 98DX3236 + bool + select ARMADA_MSYS + config 88F6820 bool select ARMADA_38X diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index ee2eca913484..2ab7b3c8417e 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -24,6 +24,7 @@ ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMADA_375) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_ARMADA_38X) += ../../../drivers/ddr/marvell/a38x/xor.o obj-$(CONFIG_ARMADA_XP) += ../../../drivers/ddr/marvell/axp/xor.o +obj-$(CONFIG_ARMADA_MSYS) += ../../../drivers/ddr/marvell/axp/xor.o obj-$(CONFIG_MVEBU_EFUSE) += efuse.o extra-y += kwbimage.cfg diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 919d05c88c77..61b222a21070 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -23,6 +23,11 @@ static struct mbus_win windows[] = { /* NOR */ { MBUS_BOOTROM_BASE, MBUS_BOOTROM_SIZE, CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM }, + +#ifdef CONFIG_ARMADA_MSYS + /* DFX */ + { MBUS_DFX_BASE, MBUS_DFX_SIZE, CPU_TARGET_DFX, 0 }, +#endif }; void lowlevel_init(void) @@ -121,6 +126,14 @@ static const struct sar_freq_modes sar_freq_tab[] = { { 0x13, 0x0, 2000, 1000, 933 }, { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ }; +#elif defined(CONFIG_ARMADA_MSYS) +static const struct sar_freq_modes sar_freq_tab[] = { + { 0x0, 0x0, 400, 400, 400 }, + { 0x2, 0x0, 667, 333, 667 }, + { 0x3, 0x0, 800, 400, 800 }, + { 0x5, 0x0, 800, 400, 800 }, + { 0xff, 0xff, 0, 0, 0 } /* 0xff marks end of array */ +}; #else /* SAR frequency values for Armada XP */ static const struct sar_freq_modes sar_freq_tab[] = { @@ -144,7 +157,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq) u32 freq; int i; -#if defined(CONFIG_ARMADA_375) +#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_MSYS) val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */ #else val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ @@ -160,7 +173,7 @@ void get_sar_freq(struct sar_freq_modes *sar_freq) #endif for (i = 0; sar_freq_tab[i].val != 0xff; i++) { if (sar_freq_tab[i].val == freq) { -#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) +#if defined(CONFIG_ARMADA_375) || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS) *sar_freq = sar_freq_tab[i]; return; #else @@ -270,6 +283,20 @@ int print_cpuinfo(void) } } + if (mvebu_soc_family() == MVEBU_SOC_MSYS) { + switch (revid) { + case 3: + puts("A0"); + break; + case 4: + puts("A1"); + break; + default: + printf("?? (%x)", revid); + break; + } + } + get_sar_freq(&sar_freq); printf(" at %d MHz\n", sar_freq.p_clk); diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index e3235fc67ecd..a14d1e3836bb 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -17,7 +17,7 @@ #include #if defined(CONFIG_ARMADA_XP) || defined(CONFIG_ARMADA_375) \ - || defined(CONFIG_ARMADA_38X) + || defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_MSYS) /* * Set this for the common xor register definitions needed in dram.c * for A38x as well here. diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h index 9e23043a4857..b9153d86c669 100644 --- a/arch/arm/mach-mvebu/include/mach/cpu.h +++ b/arch/arm/mach-mvebu/include/mach/cpu.h @@ -34,6 +34,7 @@ enum cpu_target { CPU_TARGET_PCIE02 = 0x4, CPU_TARGET_ETH01 = 0x7, CPU_TARGET_PCIE13 = 0x8, + CPU_TARGET_DFX = 0x8, CPU_TARGET_SASRAM = 0x9, CPU_TARGET_SATA01 = 0xa, /* A38X */ CPU_TARGET_NAND = 0xd, @@ -79,6 +80,8 @@ enum { #define MBUS_PCI_IO_SIZE (64 << 10) #define MBUS_SPI_BASE 0xF4000000 #define MBUS_SPI_SIZE (8 << 20) +#define MBUS_DFX_BASE 0xF6000000 +#define MBUS_DFX_SIZE (1 << 20) #define MBUS_BOOTROM_BASE 0xF8000000 #define MBUS_BOOTROM_SIZE (8 << 20) diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h index 01577f469b0e..2d88c410b88c 100644 --- a/arch/arm/mach-mvebu/include/mach/soc.h +++ b/arch/arm/mach-mvebu/include/mach/soc.h @@ -76,7 +76,11 @@ #define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000)) #define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000)) #define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000)) +#ifdef CONFIG_ARMADA_MSYS +#define MVEBU_DFX_BASE (MBUS_DFX_BASE) +#else #define MVEBU_DFX_BASE (MVEBU_REGISTER(0xe4000)) +#endif #define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200)) #define MBUS_ERR_PROP_EN (1 << 8) @@ -149,6 +153,22 @@ #define BOOT_FROM_SPI 0x32 #define BOOT_FROM_MMC 0x30 #define BOOT_FROM_MMC_ALT 0x31 +#elif defined(CONFIG_ARMADA_MSYS) +/* SAR values for MSYS */ +#define CONFIG_SAR_REG (MBUS_DFX_BASE + 0xf8200) +#define CONFIG_SAR2_REG (MBUS_DFX_BASE + 0xf8204) + +#define SAR_CPU_FREQ_OFFS 18 +#define SAR_CPU_FREQ_MASK (0x7 << SAR_CPU_FREQ_OFFS) +#define SAR_BOOT_DEVICE_OFFS 11 +#define SAR_BOOT_DEVICE_MASK (0x7 << SAR_BOOT_DEVICE_OFFS) + +#define BOOT_DEV_SEL_OFFS 11 +#define BOOT_DEV_SEL_MASK (0x7 << BOOT_DEV_SEL_OFFS) + +#define BOOT_FROM_NAND 0x1 +#define BOOT_FROM_UART 0x2 +#define BOOT_FROM_SPI 0x3 #else /* SAR values for Armada XP */ #define CONFIG_SAR_REG (MVEBU_REGISTER(0x18230)) diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c index df4c5cb2d718..3a869e09d3ba 100644 --- a/arch/arm/mach-mvebu/mbus.c +++ b/arch/arm/mach-mvebu/mbus.c @@ -344,6 +344,11 @@ static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus) } } mbus_dram_info.num_cs = cs; + +#if defined(CONFIG_ARMADA_MSYS) + /* Disable MBUS Err Prop - in order to avoid data aborts */ + clrbits_le32(mbus->mbuswins_base + 0x200, BIT(8)); +#endif } static const struct mvebu_mbus_soc_data diff --git a/drivers/ddr/marvell/axp/xor_regs.h b/drivers/ddr/marvell/axp/xor_regs.h index db5c41967393..d779e564189a 100644 --- a/drivers/ddr/marvell/axp/xor_regs.h +++ b/drivers/ddr/marvell/axp/xor_regs.h @@ -13,7 +13,11 @@ #define XOR_UNIT(chan) ((chan) >> 1) #define XOR_CHAN(chan) ((chan) & 1) +#ifdef CONFIG_ARMADA_MSYS +#define MV_XOR_REGS_OFFSET(unit) (0xF0800) +#else #define MV_XOR_REGS_OFFSET(unit) (0x60900) +#endif #define MV_XOR_REGS_BASE(unit) (MV_XOR_REGS_OFFSET(unit)) /* XOR Engine Control Register Map */