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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Y2Ku2O9LYQfW/u5omaX1wgudlDrrdetYW5bzMNVS1GvwgK74c4VhOlu6Ar09Znx/bzMT3BZRE6eedO33G00PMZ2SedAvK5gSdNIYC0yzU3HD5XzAjT3EVcTFp/GEFlfWa+UuOATOwbzCBre/wbVxmZRgZHvv+X+B0tN6F6mflX2ioo9/4nhoP8dftUk+V/xYHE1L3msRFdeaU78cK/P1NNcPp3dfK5FNHxY2aIzhQ1RBeRZKEJKQ5OIWsDCwrzgiEMzm/Oqvbk2zJYD3mK83lHHebQcpcF4cyT3hMQ357Ok8cwuCgXUThb0qUqwsuGII8ShDXqf0FtTu2oIciR2GYSCmoZAGPOMGOpPJmckvrJGyPtt+zTN0rz1UODitQBZ4EX/hc6g9ZUfW9qpmHzCf50YBIv7YsWByHx5hHX5Tu6E= MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 25c882e5-a256-4c1e-98ad-08d68b6a7ab0 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Feb 2019 13:04:32.3475 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR04MB6229 Cc: Palmer Dabbelt , U-Boot Mailing List , Alexander Graf , Christoph Hellwig Subject: [U-Boot] [PATCH v5 03/15] riscv: Rename cpu/qemu to cpu/generic X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel Reviewed-by: Alexander Graf Reviewed-by: Lukas Auer Reviewed-by: Bin Meng --- arch/riscv/Kconfig | 2 +- arch/riscv/cpu/{qemu => generic}/Kconfig | 2 +- arch/riscv/cpu/{qemu => generic}/Makefile | 0 arch/riscv/cpu/{qemu => generic}/cpu.c | 0 arch/riscv/cpu/{qemu => generic}/dram.c | 0 board/emulation/qemu-riscv/Kconfig | 4 ++-- 6 files changed, 4 insertions(+), 4 deletions(-) rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%) rename arch/riscv/cpu/{qemu => generic}/Makefile (100%) rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%) rename arch/riscv/cpu/{qemu => generic}/dram.c (100%) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c45e4d73a8..6879047ff7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -22,7 +22,7 @@ source "board/emulation/qemu-riscv/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" -source "arch/riscv/cpu/qemu/Kconfig" +source "arch/riscv/cpu/generic/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/generic/Kconfig similarity index 91% rename from arch/riscv/cpu/qemu/Kconfig rename to arch/riscv/cpu/generic/Kconfig index f48751e6de..1d6ab5032d 100644 --- a/arch/riscv/cpu/qemu/Kconfig +++ b/arch/riscv/cpu/generic/Kconfig @@ -2,7 +2,7 @@ # # Copyright (C) 2018, Bin Meng -config QEMU_RISCV +config GENERIC_RISCV bool select ARCH_EARLY_INIT_R imply CPU diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/generic/Makefile similarity index 100% rename from arch/riscv/cpu/qemu/Makefile rename to arch/riscv/cpu/generic/Makefile diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/generic/cpu.c similarity index 100% rename from arch/riscv/cpu/qemu/cpu.c rename to arch/riscv/cpu/generic/cpu.c diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/generic/dram.c similarity index 100% rename from arch/riscv/cpu/qemu/dram.c rename to arch/riscv/cpu/generic/dram.c diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 0d865acf10..88d07d568e 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "emulation" config SYS_CPU - default "qemu" + default "generic" config SYS_CONFIG_NAME default "qemu-riscv" @@ -18,7 +18,7 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select QEMU_RISCV + select GENERIC_RISCV imply SYS_NS16550 imply VIRTIO_MMIO imply VIRTIO_NET