From patchwork Tue Feb 5 05:59:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1036435 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="PqkOrWl1"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43tv7J2jVsz9sMx for ; Tue, 5 Feb 2019 17:00:12 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1FE3BC21E77; Tue, 5 Feb 2019 05:59:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 59850C21F16; Tue, 5 Feb 2019 05:59:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3314FC21E8A; Tue, 5 Feb 2019 05:59:02 +0000 (UTC) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lists.denx.de (Postfix) with ESMTPS id 1C396C21EDC for ; Tue, 5 Feb 2019 05:58:56 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x155wn16029483; Mon, 4 Feb 2019 23:58:49 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1549346329; bh=7SNMFhv+89Zpje7D957wGyr+/+VuTEdibmjxGck3I7s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=PqkOrWl1vhNYm0A3iEV1gqGxzJA24TSjwHCN6QfemDseh4/vwVY1ftZjKr95v7Dxy 5XgkL1HDOvj0PV+UDl4ruZ3Z8W5mjVv7f6VuVY6AhypfnI6Tw2czR7iJzh9o/jNYou xJDbX4ceT6Ep+HWrdxM4f0PUWVE3pLG1GRZVABSI= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x155wmRL081317 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 4 Feb 2019 23:58:49 -0600 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 4 Feb 2019 23:58:48 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 4 Feb 2019 23:58:48 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x155wVW5006226; Mon, 4 Feb 2019 23:58:43 -0600 From: Vignesh R To: Jagan Teki Date: Tue, 5 Feb 2019 11:29:11 +0530 Message-ID: <20190205055929.24168-3-vigneshr@ti.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205055929.24168-1-vigneshr@ti.com> References: <20190205055929.24168-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Marek Vasut , Tom Rini , Stefan Roese , Nobuhiro Iwamatsu , Boris Brezillon , Michal Simek , u-boot@lists.denx.de, Rajat Srivastava , Miquel Raynal Subject: [U-Boot] [PATCH v4 02/20] bitops: Fix GENMASK definition for Sandbox X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In arch/sandbox/include/asm/types.h we have Therefore for 32 bit Sandbox build BITS_PER_LONG turns out to be 32 as CONFIG_PHYS64 is not set This messes up the current logic of GENMASK macro due to mismatch b/w size of unsigned long (64 bit) and that of BITS_PER_LONG. Fix this by using CONFIG_SANDBOX_BITS_PER_LONG which is set to 64/32 based on the host machine on which its being compiled. Without this patch: GENMASK(14,0) => 0x7fffffffffff After this patch: GENMASK(14,0) => 0x7fff Signed-off-by: Vignesh R Reviewed-by: Simon Glass --- Note: this patch is merged to u-boot-dm.git at: http://git.denx.de/?p=u-boot/u-boot-dm.git;a=commitdiff;h=aba05dfb5dc673606477b4510320e95fd577d9b6 But, is not part of u-boot/master yet. Patch is required for Sandbox tests to pass once this series is merged. include/linux/bitops.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/bitops.h b/include/linux/bitops.h index a47f6d17bb5f..259df43fb00f 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -21,8 +21,13 @@ * position @h. For example * GENMASK_ULL(39, 21) gives us the 64bit vector 0x000000ffffe00000. */ +#ifdef CONFIG_SANDBOX +#define GENMASK(h, l) \ + (((~0UL) << (l)) & (~0UL >> (CONFIG_SANDBOX_BITS_PER_LONG - 1 - (h)))) +#else #define GENMASK(h, l) \ (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#endif #define GENMASK_ULL(h, l) \ (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))