| Message ID | 20190204105846.26889-4-fparent@baylibre.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | Add support for MT8516 SoCs | expand |
On Mon, 2019-02-04 at 11:58 +0100, Fabien Parent wrote: > Add the implementation for the CLK_GATE_SETCLR_INV flag. > > Signed-off-by: Fabien Parent <fparent@baylibre.com> Acked-by: Ryder Lee <ryder.lee@mediatek.com> > --- > drivers/clk/mediatek/clk-mtk.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c > index 870b14ed8b..725be031b8 100644 > --- a/drivers/clk/mediatek/clk-mtk.c > +++ b/drivers/clk/mediatek/clk-mtk.c > @@ -390,6 +390,9 @@ static int mtk_clk_gate_enable(struct clk *clk) > case CLK_GATE_SETCLR: > writel(bit, priv->base + gate->regs->clr_ofs); > break; > + case CLK_GATE_SETCLR_INV: > + writel(bit, priv->base + gate->regs->set_ofs); > + break; > case CLK_GATE_NO_SETCLR_INV: > clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit); > break;
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index 870b14ed8b..725be031b8 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -390,6 +390,9 @@ static int mtk_clk_gate_enable(struct clk *clk) case CLK_GATE_SETCLR: writel(bit, priv->base + gate->regs->clr_ofs); break; + case CLK_GATE_SETCLR_INV: + writel(bit, priv->base + gate->regs->set_ofs); + break; case CLK_GATE_NO_SETCLR_INV: clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit); break;
Add the implementation for the CLK_GATE_SETCLR_INV flag. Signed-off-by: Fabien Parent <fparent@baylibre.com> --- drivers/clk/mediatek/clk-mtk.c | 3 +++ 1 file changed, 3 insertions(+)