From patchwork Tue Jan 29 05:57:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1032509 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="oWPwq4fy"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43pbZS2jtNz9sDK for ; Tue, 29 Jan 2019 17:05:20 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 147C9C21DFF; Tue, 29 Jan 2019 06:03:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 597BAC21E15; Tue, 29 Jan 2019 05:58:57 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9969FC21DED; Tue, 29 Jan 2019 05:56:46 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lists.denx.de (Postfix) with ESMTPS id 6FDC1C21D65 for ; Tue, 29 Jan 2019 05:56:42 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x0T5ufYT081514; Mon, 28 Jan 2019 23:56:41 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1548741401; bh=Xd74+Kufzk3Oi4X4o3zr2zKdbWEqR5AvHEqoJFakqHg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oWPwq4fy1eYQ82REzlIXlqJopjevf4gOP7z9247D0d6/bBWvyVFB3lSaJ3UIx3Yn5 JKqT2Vplp6oY6uAyafUcgtFnfRntlQBbp7VjSbfT/M3qPCaPQm+AH0zJ+0V51wxE5H Nm59DHLK1r0nZsm7wyIkh+KfJ+mY6OcIZykaEhP0= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x0T5uesa041738 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 28 Jan 2019 23:56:41 -0600 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Mon, 28 Jan 2019 23:56:40 -0600 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Mon, 28 Jan 2019 23:56:40 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id x0T5uRDc016083; Mon, 28 Jan 2019 23:56:39 -0600 From: Vignesh R To: Tom Rini Date: Tue, 29 Jan 2019 11:27:28 +0530 Message-ID: <20190129055729.25553-7-vigneshr@ti.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190129055729.25553-1-vigneshr@ti.com> References: <20190129055729.25553-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 6/7] arm64: dts: ti: k3-am65: add mcu navss nodes X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Grygorii Strashko Add DT node for MCU NAVSS its components to get DMA working on AM654 SoC. Signed-off-by: Grygorii Strashko Signed-off-by: Vignesh R Reviewed-by: Tom Rini --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 46 ++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 143eb6d63092..5a934b106d04 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -4,6 +4,7 @@ */ #include +#include / { chosen { @@ -63,6 +64,51 @@ pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; + + navss_mcu: navss-mcu { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ti,sci-dev-id = <119>; + + mcu_ringacc: ringacc@2b800000 { + compatible = "ti,am654-navss-ringacc"; + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>; + reg-names = "rt", "fifos", + "proxy_gcfg", "proxy_target"; + ti,num-rings = <286>; + ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ + ti,dma-ring-reset-quirk; + ti,sci = <&dmsc>; + ti,sci-dev-id = <195>; + }; + + mcu_udmap: udmap@285c0000 { + compatible = "ti,k3-navss-udmap"; + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x2aa00000 0x0 0x40000>; + reg-names = "gcfg", "rchanrt", "tchanrt"; + #dma-cells = <3>; + + ti,ringacc = <&mcu_ringacc>; + ti,psil-base = <0x6000>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <194>; + + ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */ + <0x2>; /* TX_CHAN */ + ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */ + <0x4>; /* RX_CHAN */ + ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */ + }; + }; }; &cbass_wakeup {