From patchwork Thu Jan 17 11:03:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1026537 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="VbzNLdfl"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43gLwd3qCzz9s3l for ; Thu, 17 Jan 2019 22:10:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D5CA7C22047; Thu, 17 Jan 2019 11:06:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D7E17C220C7; Thu, 17 Jan 2019 11:05:12 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8F0BDC220C6; Thu, 17 Jan 2019 11:04:52 +0000 (UTC) Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by lists.denx.de (Postfix) with ESMTPS id D62BBC2209D for ; Thu, 17 Jan 2019 11:04:47 +0000 (UTC) Received: by mail-pf1-f196.google.com with SMTP id c73so4655256pfe.13 for ; Thu, 17 Jan 2019 03:04:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NsNz6rr6YStWvZeHsAplzXkMR8s6KSDyTxRi5k3ZCGw=; b=VbzNLdfldm8kh0F88WZwF+kUnzxmzOPY8Pf6OrZ8OrHAzlzW68K5GUV+MH+a3FbHK3 AqFVYLrCg9hlgiA0sHUC+e7k3c0Azpg4BRvznrNZfFh/C7tRx+FUfL5JMnk9ftqfdywo YtG+TcgbGvoIixN8Tu1n2HtOVujRvmdbWdYLLO3NthUvDKHsClXyZkH0waUNFNmS6kie t5UB2Nj3LhkJlQHh/jUijQQQbYg97+RDUmDzsGY18vkuLelTYxBRuxoO8/uX5ioSnJsd QWeCgP7J5YdAA+yI+0qqUWwjtSDUROEDuN6x68iZSQWtNLHg08S7oImMXUTwK/4i+9lr SAsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NsNz6rr6YStWvZeHsAplzXkMR8s6KSDyTxRi5k3ZCGw=; b=DUqYX/LVBMAp7xgg60G9YRALTjSr6a5+Hp35+K/5yh7YJRJ073NqkXI9m/OTplzs48 mygckllk4cZrxI5Q/axzNSMo811iI5eRjSGGpo8KzCAC1IRCoVQPeAlibpGZkggIw8i2 Pw6XLtwCx/800xAsBYMo0FRzS+ElfNhqHEdcvIyQuUOOaPvshHuLyUcuaLDWkIv9M5WL JC4eZL3MJzOtBeTFkcIkR6Kd4Esrayqx9+U4DVKzf8yrB0/P3dxL2RP+AK6Io1Afvcp4 SAy1PPW1eXZ2XoDkGPra5MFSkYF4p4pQTSalvk+XnBbQYtWtRj4lDFHr13U9jTCZ6+C5 Q8ng== X-Gm-Message-State: AJcUukf1V14447bgsVMpPJmFFZOwYy1ZrW1kGPKfIJM/ovf5daC2be+P ZITuxSWKCfU3nLRnDNZNsdLOnQ== X-Google-Smtp-Source: ALg8bN6fEhfQJ4TFgw2lHiHi7g8dFIk6UPRxIbXMAl79tF/ovploFCkEOfFEo10US5pr4w3VhdBr2w== X-Received: by 2002:a63:e711:: with SMTP id b17mr12666984pgi.363.1547723086319; Thu, 17 Jan 2019 03:04:46 -0800 (PST) Received: from localhost.localdomain ([106.51.16.164]) by smtp.gmail.com with ESMTPSA id h15sm1688142pgl.43.2019.01.17.03.04.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Jan 2019 03:04:45 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Joe Hershberger , Lukas Auer , Masahiro Yamada , Simon Glass Date: Thu, 17 Jan 2019 16:33:52 +0530 Message-Id: <20190117110356.36753-8-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190117110356.36753-1-anup@brainfault.org> References: <20190117110356.36753-1-anup@brainfault.org> Cc: Palmer Dabbelt , U-Boot Mailing List , Alexander Graf , Christoph Hellwig , Paul Walmsley Subject: [U-Boot] [PATCH 07/11] clk: Add fixed-factor clock driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Anup Patel This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: Anup Patel Signed-off-by: Atish Patra --- drivers/clk/Makefile | 4 +- drivers/clk/clk_fixed_factor.c | 74 ++++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/clk_fixed_factor.c diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 2f4446568c..fa59259ea3 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -4,7 +4,9 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o +obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o obj-y += imx/ obj-y += tegra/ diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c new file mode 100644 index 0000000000..eab1724c26 --- /dev/null +++ b/drivers/clk/clk_fixed_factor.c @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Author: Anup Patel + */ + +#include +#include +#include +#include + +struct clk_fixed_factor { + struct clk parent; + unsigned int div; + unsigned int mult; +}; + +#define to_clk_fixed_factor(dev) \ + ((struct clk_fixed_factor *)dev_get_platdata(dev)) + +static ulong clk_fixed_factor_get_rate(struct clk *clk) +{ + int ret; + struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev); + + if (clk->id != 0) + return -EINVAL; + + ret = clk_get_rate(&ff->parent); + if (IS_ERR_VALUE(ret)) + return ret; + + do_div(ret, ff->div); + + return ret * ff->mult; +} + +const struct clk_ops clk_fixed_factor_ops = { + .get_rate = clk_fixed_factor_get_rate, +}; + +static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + int err; + struct clk_fixed_factor *ff = to_clk_fixed_factor(dev); + + err = clk_get_by_index(dev, 0, &ff->parent); + if (err) + return err; + + ff->div = dev_read_u32_default(dev, "clock-div", 1); + ff->mult = dev_read_u32_default(dev, "clock-mult", 1); +#endif + + return 0; +} + +static const struct udevice_id clk_fixed_factor_match[] = { + { + .compatible = "fixed-factor-clock", + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(clk_fixed_factor) = { + .name = "fixed_factor_clock", + .id = UCLASS_CLK, + .of_match = clk_fixed_factor_match, + .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor), + .ops = &clk_fixed_factor_ops, +};