From patchwork Thu Jan 17 11:03:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1026528 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="oFs5SZW6"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43gLrD33BQz9s3l for ; Thu, 17 Jan 2019 22:07:08 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1AE79C21F41; Thu, 17 Jan 2019 11:05:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D2C1DC21FD1; Thu, 17 Jan 2019 11:04:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 78D0AC2209D; Thu, 17 Jan 2019 11:04:29 +0000 (UTC) Received: from mail-pf1-f194.google.com (mail-pf1-f194.google.com [209.85.210.194]) by lists.denx.de (Postfix) with ESMTPS id C49FBC220C7 for ; Thu, 17 Jan 2019 11:04:25 +0000 (UTC) Received: by mail-pf1-f194.google.com with SMTP id z9so4683711pfi.2 for ; Thu, 17 Jan 2019 03:04:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=CsPN65eCnjMkqvCuOuLjmT9avaqpZPNfNpC9FuoQrgo=; b=oFs5SZW6jtu0K6WqhLLBbDE1z9BifuWsQTLEKAUoSYurpceIbKguwKhdRrJm9OHORS OVnOrp5HZhEIYGNQDnGrhjanyX10M56TmlufM1W/Jgs9tj+LTGyD/Ol3TmH0lDLu0QCT 7wQxyvdMWY7hZJTElCp1EifxiN59tYYY0ko6G6jNWvBPM6eMaTbrAM4S6QoGf34yGQ37 IW2Bu3cBtvaPS2bKVAbFBWDE7UuObjjUDaN2XyqocpFt80LSNPkPPeElcPcv3fFp4Z8I Y+VK2eaL4ixccjzIQuylzLvLGDvBU1/+RxeCcWv4QnaWEruUFUQmo3zS+gS6bt016OkQ YmZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CsPN65eCnjMkqvCuOuLjmT9avaqpZPNfNpC9FuoQrgo=; b=O3fq6gFbLYgWCGe4PYHBNXQU4uTf1iSODICuWM9laoo730rDn1t/gxb1mXQ9Q+iHa0 m3nGv1jylj0T6zcCuF7/QTWUGG3V+NKKLW48QeJJKrr/2X+2jQiK2du0L+Naa68J9SWL boOjJTPbnLw6MwT5kxHYcVQ8H6YvrXIYDWmyC9yOHBU37lh7kVl0sC3OQzjEe+kZkK41 12Rjui+KV7X3om2SbJ3aaTM7S6uQ8uMR8mYsSDYDyvIpHbN/D4LUy73hh1QLmK3yyFNy Ia+TYCok2942AV9j3kZl20uYl+Aw/Zo/gC88Z3qSJXti7P0mHI8UNEp33uX+LSeq28Ns iYzw== X-Gm-Message-State: AJcUukdbnxpSr6Qp1Vx+4Ua9fHHH0LYUw01keTowmRSPOcNBaU1TAkE5 IOEZ89eEQjPTXWsGijbdCRbhSw== X-Google-Smtp-Source: ALg8bN7ffmb8cUp6Qm3dCFsQNQln+Z567fncTokbdXP22kHt9/ZigpOvkuEY0UdJRhOoDw9hz67m7A== X-Received: by 2002:a65:5c02:: with SMTP id u2mr12944274pgr.13.1547723064309; Thu, 17 Jan 2019 03:04:24 -0800 (PST) Received: from localhost.localdomain ([106.51.16.164]) by smtp.gmail.com with ESMTPSA id h15sm1688142pgl.43.2019.01.17.03.04.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Jan 2019 03:04:23 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Joe Hershberger , Lukas Auer , Masahiro Yamada , Simon Glass Date: Thu, 17 Jan 2019 16:33:48 +0530 Message-Id: <20190117110356.36753-4-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190117110356.36753-1-anup@brainfault.org> References: <20190117110356.36753-1-anup@brainfault.org> Cc: Palmer Dabbelt , U-Boot Mailing List , Alexander Graf , Christoph Hellwig , Paul Walmsley Subject: [U-Boot] [PATCH 03/11] riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Anup Patel On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot DMA mapping APIs will generate DMA addresses beyond 4GB. This breaks DMA programming in 32bit DMA capable devices (such as Cadence MACB ethernet). For example, If DRAM is more then 2GB on QEMU sifive_u machine then Cadence MACB ethernet stops working for U-Boot because it is a 32bit DMA capable device. To handle 32bit DMA capable devices on 64bit systems, we provide custom implementation of board_get_usable_ram_top() which ensures that usable ram top is not more then 4GB. This in-turn ensures that U-Boot always runs within 4GB hence DMA addresses generated by DMA mapping APIs will be within 4GB too. Signed-off-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/cpu/generic/dram.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 84d87d2a7f..dea2d3701d 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -6,6 +6,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + int dram_init(void) { return fdtdec_setup_mem_size_base(); @@ -15,3 +17,23 @@ int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); } + +ulong board_get_usable_ram_top(ulong total_size) +{ +#ifdef CONFIG_64BIT + /* + * Ensure that we run from first 4GB so that all + * addresses used by U-Boot are 32bit addresses. + * + * This in-turn ensures that 32bit DMA capabale + * devices work fine because DMA mapping APIs will + * provide 32bit DMA addresses only. + */ + if (gd->ram_top > 0x100000000UL) + return 0x100000000UL; + else + return gd->ram_top; +#else + return gd->ram_top; +#endif +}