From patchwork Thu Jan 17 11:03:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1026524 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="DivRH09h"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43gLnd27dQz9s3l for ; Thu, 17 Jan 2019 22:04:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E88A7C220D4; Thu, 17 Jan 2019 11:04:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 20DC8C220AE; Thu, 17 Jan 2019 11:04:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 95E2EC21F41; Thu, 17 Jan 2019 11:04:20 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id 8565BC22047 for ; Thu, 17 Jan 2019 11:04:15 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id z23so4611798plo.0 for ; Thu, 17 Jan 2019 03:04:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2btUZma3RH8L1qZ/ko2z2YQYLHVo6bAQ2y9nHE2tO4M=; b=DivRH09hie7npP6fJUO1kGhB36R4N1O4BNdhkGCfrBY3iaCSrAEXH05nIy5xIHn2Jp BOkOTypHt1dAJpSCDqPja4b9Ai8yh2KmxWEwJf77019sSe3S34R3nt14Skq1a12vNfB4 9/1P75fyUnl4FjUFHTlzHVcM9xQ8BbphIVu1C7Tq1EGyQk5cAaqKfQXSCDntLTdkbAwF /wLT7Uy8h9Eiw6OHMaxJlfwGkVaWoTGMkokcRhrW/EyMaSCPAFlyaEhBSs/vgAL5jVuu B562OnACi5gls1PP+rM07wLX8UZ9kSY1xyIHCO71LTLG9AqKM59c/bvg9bOZVq1g9KWX wPHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2btUZma3RH8L1qZ/ko2z2YQYLHVo6bAQ2y9nHE2tO4M=; b=XlpJ7Gm2QxW1ZWBjqqgFQT+5FIoZxiqdy5Q7LgntuQ69kwa3Igk6xVY16ZpFP86s9Z 3QaFv08AWSqSHvVkYSEShVNOxWXLVhclU/RZ9YoelZbVD4UC1vi3Ky96lmwRx72TkDTF WssauT370mAM97AoJ9hkIf1gFw8Slu79PQ62wSgtW2ZP3/B6u+2WKiJgy7p6oXDBihsb k805r51nCjXBCWFgjMVG7hUvZNWcXRIH/CyQ2XBWE6hi0lz8CE9aDpqcpQ6Paje95IBC 6VZ0W+hz67b4lSoYKmaS0Ki1Ecxb/v6vN707AFARtKF1y5womSRq55pWCBx4LI29ZpX2 YVjA== X-Gm-Message-State: AJcUuke8/7CMLw0ZIR1WG6EXcd5uWm4onG4WSiliXkTSLwF1RWfTrnBb /bQMjcjVzXqXn9JgMgDPPwUVJQ== X-Google-Smtp-Source: ALg8bN6iwe9ksaSFMZ7ABWeVdKNW5buDinDMVuSPM2v5cKExm2Gg2hD2tTmlH2f1oxL2rZ4SsMEaNA== X-Received: by 2002:a17:902:6909:: with SMTP id j9mr14165873plk.196.1547723053794; Thu, 17 Jan 2019 03:04:13 -0800 (PST) Received: from localhost.localdomain ([106.51.16.164]) by smtp.gmail.com with ESMTPSA id h15sm1688142pgl.43.2019.01.17.03.04.09 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Jan 2019 03:04:13 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Joe Hershberger , Lukas Auer , Masahiro Yamada , Simon Glass Date: Thu, 17 Jan 2019 16:33:46 +0530 Message-Id: <20190117110356.36753-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190117110356.36753-1-anup@brainfault.org> References: <20190117110356.36753-1-anup@brainfault.org> Cc: Palmer Dabbelt , U-Boot Mailing List , Alexander Graf , Christoph Hellwig , Paul Walmsley Subject: [U-Boot] [PATCH 01/11] riscv: Rename cpu/qemu to cpu/generic X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Anup Patel The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine. This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 2 +- arch/riscv/cpu/{qemu => generic}/Kconfig | 2 +- arch/riscv/cpu/{qemu => generic}/Makefile | 0 arch/riscv/cpu/{qemu => generic}/cpu.c | 0 arch/riscv/cpu/{qemu => generic}/dram.c | 0 board/emulation/qemu-riscv/Kconfig | 4 ++-- 6 files changed, 4 insertions(+), 4 deletions(-) rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%) rename arch/riscv/cpu/{qemu => generic}/Makefile (100%) rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%) rename arch/riscv/cpu/{qemu => generic}/dram.c (100%) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c45e4d73a8..6879047ff7 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -22,7 +22,7 @@ source "board/emulation/qemu-riscv/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" -source "arch/riscv/cpu/qemu/Kconfig" +source "arch/riscv/cpu/generic/Kconfig" # architecture-specific options below diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/generic/Kconfig similarity index 91% rename from arch/riscv/cpu/qemu/Kconfig rename to arch/riscv/cpu/generic/Kconfig index f48751e6de..1d6ab5032d 100644 --- a/arch/riscv/cpu/qemu/Kconfig +++ b/arch/riscv/cpu/generic/Kconfig @@ -2,7 +2,7 @@ # # Copyright (C) 2018, Bin Meng -config QEMU_RISCV +config GENERIC_RISCV bool select ARCH_EARLY_INIT_R imply CPU diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/generic/Makefile similarity index 100% rename from arch/riscv/cpu/qemu/Makefile rename to arch/riscv/cpu/generic/Makefile diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/generic/cpu.c similarity index 100% rename from arch/riscv/cpu/qemu/cpu.c rename to arch/riscv/cpu/generic/cpu.c diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/generic/dram.c similarity index 100% rename from arch/riscv/cpu/qemu/dram.c rename to arch/riscv/cpu/generic/dram.c diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 0d865acf10..88d07d568e 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -7,7 +7,7 @@ config SYS_VENDOR default "emulation" config SYS_CPU - default "qemu" + default "generic" config SYS_CONFIG_NAME default "qemu-riscv" @@ -18,7 +18,7 @@ config SYS_TEXT_BASE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select QEMU_RISCV + select GENERIC_RISCV imply SYS_NS16550 imply VIRTIO_MMIO imply VIRTIO_NET