From patchwork Thu Jan 17 11:03:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1026539 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="uqS1ASXV"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43gLxp6vt6z9s3l for ; Thu, 17 Jan 2019 22:11:58 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A20A0C220D4; Thu, 17 Jan 2019 11:08:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2BC18C220C7; Thu, 17 Jan 2019 11:06:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 73700C220C0; Thu, 17 Jan 2019 11:05:14 +0000 (UTC) Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) by lists.denx.de (Postfix) with ESMTPS id 4C307C220E1 for ; Thu, 17 Jan 2019 11:05:08 +0000 (UTC) Received: by mail-pg1-f196.google.com with SMTP id t13so4288994pgr.11 for ; Thu, 17 Jan 2019 03:05:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=B48AGffxaNERKz+eaLcM4c7eMx7Ue4zsBT3wPMXjpUU=; b=uqS1ASXVew98T1msvLlf93OwQivdjvF8tto8Arr+HZxpWZTWXl+GQW0jSwvkkg6xH3 eUsOmPYpSCS+9FgeTCwYgUSVI83rxSUMNgOlMxmITIZI/XhRUZnEDDFH+2e88zsnMlem 3xW1fwS3h/yxKRm2xkWK7a1Vvf44tPJZ5GlqGCNDt09lZ0CPKXKe8kVXbuxv9Lv51B7f yCRwltWDnKDpo6A7yIBvWigl/iH0kDm6efxyo5wSw+Z/xcBWYvE5ljZmkdx4mUYKIiHm Y6juLWhbZUPaoRZoUqSbU1QfeU+zb2W45htl02cXYNqQpL0PlyLetGsraGZhytg4kRr9 HV5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=B48AGffxaNERKz+eaLcM4c7eMx7Ue4zsBT3wPMXjpUU=; b=Cghy2ghSLi/Rpeg1wvpMe2j5lFaKd2Aq3y+W++6GRiNkC3EKKtcV0kXXjDQiTHeC9u rHSgOHFzEB9tUIV0ZhGIMPWyR0eaSuJXyPgIDk92fiGBPZsYFkoYGwvR2FyMKO0v+bU7 ox4/UOvHuS1nmF0oIxh+XWx0WNfKk+vwp4tMihgc31o5WdgRUsSbS0x158xk7EgBJODX ebR/MgAnw6UMxiKFnBIN2tz53bU1R7rXRTQV3leesF0nO+6BlL0nYsDYGwh2FWM8ibld EoHpo872Ns1r4p4W31Rbh1H8STKxJowUenUgKoI9JuSgnUCwIQ+Fwd3IcZJve9WEaJZl dDEA== X-Gm-Message-State: AJcUukdtQTsrjVzGoVvtLnlrHxf7eyvNlCYMX/d3MnlOKDOVD0QuIJMz vi/Ej045RXM+zFM1ztG4i5nVWA== X-Google-Smtp-Source: ALg8bN7q1faTE4hPhqYv9R8bYWVVI0VyJjfEK5ab+1OxvuG1AMXyHkPCT3lexNXHfFew/akeh31QqA== X-Received: by 2002:a63:fe0a:: with SMTP id p10mr12909587pgh.265.1547723106754; Thu, 17 Jan 2019 03:05:06 -0800 (PST) Received: from localhost.localdomain ([106.51.16.164]) by smtp.gmail.com with ESMTPSA id h15sm1688142pgl.43.2019.01.17.03.05.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Jan 2019 03:05:06 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Joe Hershberger , Lukas Auer , Masahiro Yamada , Simon Glass Date: Thu, 17 Jan 2019 16:33:56 +0530 Message-Id: <20190117110356.36753-12-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190117110356.36753-1-anup@brainfault.org> References: <20190117110356.36753-1-anup@brainfault.org> Cc: Palmer Dabbelt , U-Boot Mailing List , Alexander Graf , Christoph Hellwig , Paul Walmsley Subject: [U-Boot] [PATCH 11/11] riscv: Add SiFive FU540 board support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Anup Patel This patch adds SiFive FU540 board support. For now, only SiFive serial, SiFive PRCI, and Cadance MACB drivers are only enabled. The SiFive FU540 defconfig by default builds U-Boot for S-Mode because U-Boot on SiFive FU540 will run in S-Mode as payload of BBL or OpenSBI. Signed-off-by: Anup Patel Signed-off-by: Atish Patra --- arch/riscv/Kconfig | 4 ++++ board/sifive/fu540/Kconfig | 42 +++++++++++++++++++++++++++++++++ board/sifive/fu540/MAINTAINERS | 9 +++++++ board/sifive/fu540/Makefile | 5 ++++ board/sifive/fu540/fu540.c | 17 ++++++++++++++ configs/sifive_fu540_defconfig | 11 +++++++++ include/configs/sifive-fu540.h | 43 ++++++++++++++++++++++++++++++++++ 7 files changed, 131 insertions(+) create mode 100644 board/sifive/fu540/Kconfig create mode 100644 board/sifive/fu540/MAINTAINERS create mode 100644 board/sifive/fu540/Makefile create mode 100644 board/sifive/fu540/fu540.c create mode 100644 configs/sifive_fu540_defconfig create mode 100644 include/configs/sifive-fu540.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6879047ff7..36512a8995 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -14,11 +14,15 @@ config TARGET_AX25_AE350 config TARGET_QEMU_VIRT bool "Support QEMU Virt Board" +config TARGET_SIFIVE_FU540 + bool "Support SiFive FU540 Board" + endchoice # board-specific options below source "board/AndesTech/ax25-ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" +source "board/sifive/fu540/Kconfig" # platform-specific options below source "arch/riscv/cpu/ax25/Kconfig" diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig new file mode 100644 index 0000000000..6be3d88144 --- /dev/null +++ b/board/sifive/fu540/Kconfig @@ -0,0 +1,42 @@ +if TARGET_SIFIVE_FU540 + +config SYS_BOARD + default "fu540" + +config SYS_VENDOR + default "sifive" + +config SYS_CPU + default "generic" + +config SYS_CONFIG_NAME + default "sifive-fu540" + +config SYS_TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select GENERIC_RISCV + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_NET + imply CMD_PING + imply CLK_SIFIVE + imply CLK_SIFIVE_FU540_PRCI + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply MACB + imply MII + imply NET_RANDOM_ETHADDR + imply PHY_LIB + imply PHY_MSCC + imply SIFIVE_SERIAL + +endif diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS new file mode 100644 index 0000000000..702d803ad8 --- /dev/null +++ b/board/sifive/fu540/MAINTAINERS @@ -0,0 +1,9 @@ +SiFive FU540 BOARD +M: Paul Walmsley +M: Palmer Dabbelt +M: Anup Patel +M: Atish Patra +S: Maintained +F: board/sifive/fu540/ +F: include/configs/sifive-fu540.h +F: configs/sifive_fu540_defconfig diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile new file mode 100644 index 0000000000..6e1862c475 --- /dev/null +++ b/board/sifive/fu540/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (c) 2019 Western Digital Corporation or its affiliates. + +obj-y += fu540.o diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c new file mode 100644 index 0000000000..5adc4a3d4a --- /dev/null +++ b/board/sifive/fu540/fu540.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#include +#include + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig new file mode 100644 index 0000000000..2f8cca9de0 --- /dev/null +++ b/configs/sifive_fu540_defconfig @@ -0,0 +1,11 @@ +CONFIG_RISCV=y +CONFIG_TARGET_SIFIVE_FU540=y +CONFIG_RISCV_SMODE=y +CONFIG_ARCH_RV64I=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_CMD_MII=y +CONFIG_OF_PRIOR_STAGE=y diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h new file mode 100644 index 0000000000..7007b5f6af --- /dev/null +++ b/include/configs/sifive-fu540.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) + +#define CONFIG_SYS_MALLOC_LEN SZ_8M + +#define CONFIG_SYS_BOOTM_LEN SZ_16M + +#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 + +/* Environment options */ +#define CONFIG_ENV_SIZE SZ_4K + +#define BOOT_TARGET_DEVICES(func) \ + func(DHCP, dhcp, na) + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x80600000\0" \ + "fdt_addr_r=0x82200000\0" \ + "scriptaddr=0x82300000\0" \ + "pxefile_addr_r=0x82400000\0" \ + "ramdisk_addr_r=0x82500000\0" \ + BOOTENV + +#endif /* __CONFIG_H */