From patchwork Thu Jan 17 11:03:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1026540 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="rgrlfOfC"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43gLyF5HFzz9s3l for ; Thu, 17 Jan 2019 22:12:21 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3AAB7C21FD1; Thu, 17 Jan 2019 11:07:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=KHOP_BIG_TO_CC, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2FBD3C21D8A; Thu, 17 Jan 2019 11:06:36 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C9569C2209D; Thu, 17 Jan 2019 11:05:08 +0000 (UTC) Received: from mail-pg1-f194.google.com (mail-pg1-f194.google.com [209.85.215.194]) by lists.denx.de (Postfix) with ESMTPS id 58F65C2206D for ; Thu, 17 Jan 2019 11:05:03 +0000 (UTC) Received: by mail-pg1-f194.google.com with SMTP id z10so4303514pgp.7 for ; Thu, 17 Jan 2019 03:05:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WDjjAhF/zPf1gL7dq/fs0C3KNaoRYrrgMBiCuT1Exug=; b=rgrlfOfCAiedTdCf5eotnP4dhQsaUpzVkaGxI/GTcZgWIhiTgSSgeBkPxy/ROj2spy LTCh4cTihzHtpHsym6w4pY/q7mLXbcFOALrFzH5f5m4wO43HS97LWH8MWJlifphbvfyX kH0aZbh7EXpIOK3LZljIxoBrUPhEbcQmMZR2sPAhNsYtdeikuwcrdn23IGkFxOKv3QKp NtHNWPXXfQO+m0k0V/KXokcUlhBRRq8dEwYqDXfLf+SQ7oUiw80q5l1J4lTsDHbBUXCh HuakjJFMZcLMNyBL6XOjpIctKbLVcK8qdGQtOgIciT1gUMsvN6NEZpxrWVSceGZv8DWH YxDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WDjjAhF/zPf1gL7dq/fs0C3KNaoRYrrgMBiCuT1Exug=; b=j4IFtH87vD9AmXeW+dWdwbmzVafUiv0ARZHkHGiadHT5ZnScDyVDz7NcxQYhvAvQMr Ir1wFkr1pMy/wEc0eEfyRui4H52nHU5wM8UagLfTt+jV9pyIhBC0Sg5mgyMK/2u1a01r Sef+b8F6jkUOeoOC7m8lC/nKrHwx5XnaVtk6LV9OdYHUqPoGxOlkF4vEeQH2UJEwhwtl 2x37i4BKdIRUHgpkpjV+HRGNKHBFONwV2JbjPD8gl7TIdGtF/DQ8dx6m942mUabDoyCZ YXundqJG+g8QYdH6y2up3ZDLbxGLo6EqZdYqWJIWC5Sje/I69dZXJ4MGqT3InEgSGzdV q2sw== X-Gm-Message-State: AJcUukc1MHdu9/x7SqVbrJ79R/qOUQWPdUWbVn6zKizdT2APEv+trbsg dXvqADdJrqo7X4cKM2h9Mm+z6A== X-Google-Smtp-Source: ALg8bN5TaMKsIUPnCPc0daTaVl44w2BdSiUqUH5Nxc/KDZoOA76zZjgJpnpABjAJvY+SDDZzECpuNQ== X-Received: by 2002:a62:f907:: with SMTP id o7mr14314656pfh.244.1547723101793; Thu, 17 Jan 2019 03:05:01 -0800 (PST) Received: from localhost.localdomain ([106.51.16.164]) by smtp.gmail.com with ESMTPSA id h15sm1688142pgl.43.2019.01.17.03.04.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 17 Jan 2019 03:05:01 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Joe Hershberger , Lukas Auer , Masahiro Yamada , Simon Glass Date: Thu, 17 Jan 2019 16:33:55 +0530 Message-Id: <20190117110356.36753-11-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190117110356.36753-1-anup@brainfault.org> References: <20190117110356.36753-1-anup@brainfault.org> Cc: Palmer Dabbelt , U-Boot Mailing List , Alexander Graf , Christoph Hellwig , Paul Walmsley Subject: [U-Boot] [PATCH 10/11] cpu: Bind timer driver for boot hart X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Atish Patra Currently, timer driver is bound only for hart0. There is no mandatory requirement that hart0 should always come up. In fact, HiFive Unleashed SoC hart0 doesn't boot in S-mode because it only has M-mode. The timer driver should be bound for boot hart. Signed-off-by: Atish Patra --- drivers/cpu/riscv_cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 5e15df590e..f77c126499 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -10,6 +10,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size) { const char *isa; @@ -62,7 +64,6 @@ static int riscv_cpu_bind(struct udevice *dev) /* save the hart id */ plat->cpu_id = dev_read_addr(dev); - /* first examine the property in current cpu node */ ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); /* if not found, then look at the parent /cpus node */ @@ -71,7 +72,7 @@ static int riscv_cpu_bind(struct udevice *dev) &plat->timebase_freq); /* - * Bind riscv-timer driver on hart 0 + * Bind riscv-timer driver on boot hart. * * We only instantiate one timer device which is enough for U-Boot. * Pass the "timebase-frequency" value as the driver data for the @@ -80,7 +81,7 @@ static int riscv_cpu_bind(struct udevice *dev) * Return value is not checked since it's possible that the timer * driver is not included. */ - if (!plat->cpu_id && plat->timebase_freq) { + if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) { drv = lists_driver_lookup_name("riscv_timer"); if (!drv) { debug("Cannot find the timer driver, not included?\n");