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Thu, 17 Jan 2019 10:39:21 +0000 Received: from BYAPR04MB5303.namprd04.prod.outlook.com ([fe80::add1:92cc:65d7:5d94]) by BYAPR04MB5303.namprd04.prod.outlook.com ([fe80::add1:92cc:65d7:5d94%2]) with mapi id 15.20.1537.018; Thu, 17 Jan 2019 10:39:21 +0000 From: Anup Patel To: Rick Chen , Bin Meng , Joe Hershberger , Lukas Auer , Masahiro Yamada , Simon Glass Thread-Topic: [PATCH 10/11] cpu: Bind timer driver for boot hart Thread-Index: AQHUrlDorhk96hZLqEGkn14IlawYrA== Date: Thu, 17 Jan 2019 10:39:21 +0000 Message-ID: <20190117103748.36613-11-anup.patel@wdc.com> References: <20190117103748.36613-1-anup.patel@wdc.com> In-Reply-To: <20190117103748.36613-1-anup.patel@wdc.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: MA1PR0101CA0069.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:20::31) To BYAPR04MB5303.namprd04.prod.outlook.com (2603:10b6:a03:c8::20) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.17.1 x-originating-ip: [106.51.16.164] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; 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H:BYAPR04MB5303.namprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: SpawcT0jjXqXkF4iPdqqAL1pZ3b8w/u6//pPAUhr5bR3S8m6FuAVriVWsf/itHus8bviV9UVomqiCtirI1r4nXe6xwthT1ZF5vW+5MHjS7G3y9fBqYAw7k7z9GizllE0oEWu3SI/JRG6OP62j2vmjsTlUDQnwpG3rZL95yPP3ieF9MWl9rra8zv+xhGAzD/p2S+K3IqN/VKV5fBQnqAsDWqfhLNk7W1nfxUTZ2QGDA9Mw9oFmFhA2iWlTjFaHepj55SGn2kw5ghk6AdRL5uCeMenFflxNHvbiSBIW7nmxGh2W8YjeqtinXp5CWmpBpzqiSE4sTKkIqeP1dY72tJMWmu/bsze+TUQmP7CIuzTOOsi6d/Us+rOqcVgeHa6DuUzE+o9E7lxt0zCcFL52xTfu1oOOlX5LqB01nTgKWSjFS8= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 27ad99d0-dd61-4ea6-75ae-08d67c680a41 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jan 2019 10:39:17.6414 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR04MB4744 X-Mailman-Approved-At: Thu, 17 Jan 2019 12:20:43 +0000 Cc: Palmer Dabbelt , U-Boot Mailing List , Alexander Graf , Christoph Hellwig , Paul Walmsley Subject: [U-Boot] [PATCH 10/11] cpu: Bind timer driver for boot hart X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Atish Patra Currently, timer driver is bound only for hart0. There is no mandatory requirement that hart0 should always come up. In fact, HiFive Unleashed SoC hart0 doesn't boot in S-mode because it only has M-mode. The timer driver should be bound for boot hart. Signed-off-by: Atish Patra Reviewed-by: Alexander Graf --- drivers/cpu/riscv_cpu.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c index 5e15df590e..f77c126499 100644 --- a/drivers/cpu/riscv_cpu.c +++ b/drivers/cpu/riscv_cpu.c @@ -10,6 +10,8 @@ #include #include +DECLARE_GLOBAL_DATA_PTR; + static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size) { const char *isa; @@ -62,7 +64,6 @@ static int riscv_cpu_bind(struct udevice *dev) /* save the hart id */ plat->cpu_id = dev_read_addr(dev); - /* first examine the property in current cpu node */ ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); /* if not found, then look at the parent /cpus node */ @@ -71,7 +72,7 @@ static int riscv_cpu_bind(struct udevice *dev) &plat->timebase_freq); /* - * Bind riscv-timer driver on hart 0 + * Bind riscv-timer driver on boot hart. * * We only instantiate one timer device which is enough for U-Boot. * Pass the "timebase-frequency" value as the driver data for the @@ -80,7 +81,7 @@ static int riscv_cpu_bind(struct udevice *dev) * Return value is not checked since it's possible that the timer * driver is not included. */ - if (!plat->cpu_id && plat->timebase_freq) { + if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) { drv = lists_driver_lookup_name("riscv_timer"); if (!drv) { debug("Cannot find the timer driver, not included?\n");