From patchwork Fri Jan 4 00:37:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 1020559 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43W5Yx1WVmz9s7T for ; Fri, 4 Jan 2019 11:41:09 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CBD3FC21DB6; Fri, 4 Jan 2019 00:38:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BCECDC21DF9; Fri, 4 Jan 2019 00:38:04 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3C2CAC21C93; Fri, 4 Jan 2019 00:38:02 +0000 (UTC) Received: from mail-edgeDD24.fraunhofer.de (mail-edgeDD24.fraunhofer.de [192.102.167.24]) by lists.denx.de (Postfix) with ESMTPS id DD904C21C2C for ; Fri, 4 Jan 2019 00:38:01 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2GtAAAO4PJb/xoBYJliGgEBAQEBAgEBAQEHAgEBAQGBZQKCAoFWOYxvix2bPQ2EbAKDbiI4EgEDAQECAQECAgJpKEIWAYRlBjIBRhBRPRoGDgWDIYIBAah8ihwJAYdQhCuBVz+JboUOAosIlGcHAoERgQkEjn4LGIlYhyUsl2qBXSKBVTMaJIM7gicXjh0+ATIBi3GCagEB X-IPAS-Result: A2GtAAAO4PJb/xoBYJliGgEBAQEBAgEBAQEHAgEBAQGBZQKCAoFWOYxvix2bPQ2EbAKDbiI4EgEDAQECAQECAgJpKEIWAYRlBjIBRhBRPRoGDgWDIYIBAah8ihwJAYdQhCuBVz+JboUOAosIlGcHAoERgQkEjn4LGIlYhyUsl2qBXSKBVTMaJIM7gicXjh0+ATIBi3GCagEB X-IronPort-AV: E=Sophos;i="5.56,253,1539640800"; d="scan'208";a="22609578" Received: from mail-mtaka26.fraunhofer.de ([153.96.1.26]) by mail-edgeDD24.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Jan 2019 01:38:00 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0DkAACO3/Jb/xBhWMBiGwEBAQEDAQEBBwMBAQGBZYM5ITmMb6ZaDYRsAoQPOBIBAwEBAgEBAm0ohT0GMgFGEFE9GgYOBYMhggKodoocCQGHUIYCP4luhQ4CiwiUZwcCgRGBCQSOfgsYiViHJSyXaoFdIYFVMxokgzuCJxeOHT4DMAGOWwEB X-IronPort-AV: E=Sophos;i="5.56,253,1539640800"; d="scan'208";a="25618102" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP12EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA26.fraunhofer.de with ESMTP/TLS/AES256-SHA; 04 Jan 2019 01:38:01 +0100 Received: from localhost.de (10.80.233.51) by FGDEMUCIMP12EXC.ads.fraunhofer.de (10.80.232.43) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 4 Jan 2019 01:38:01 +0100 From: Lukas Auer To: Date: Fri, 4 Jan 2019 01:37:30 +0100 Message-ID: <20190104003734.28052-4-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190104003734.28052-1-lukas.auer@aisec.fraunhofer.de> References: <20190104003734.28052-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24328.005 X-TM-AS-Result: No-1.057900-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Greentime Hu Subject: [U-Boot] [PATCH v2 3/7] riscv: use invalidate/flush_*cache_range functions in cache.c X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The flush_cache() function in lib/cache.c ignores its arguments and flushes the complete data and instruction caches. Use the invalidate/flush_*cache_range() functions instead to only flush the requested memory region. This patch does not change the current behavior of U-Boot, since the implementation of the invalidate/flush_*cache_range() functions flush the complete data and instruction caches. It is in preparation for CPUs with the necessary functionality for flushing a selectable memory range. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: - New patch "riscv: use invalidate/flush_*cache_range functions in cache.c" arch/riscv/lib/cache.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 78b19da2c5..5437a122a1 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -40,8 +40,8 @@ void cache_flush(void) void flush_cache(unsigned long addr, unsigned long size) { - invalidate_icache_all(); - flush_dcache_all(); + invalidate_icache_range(addr, addr + size); + flush_dcache_range(addr, addr + size); } __weak void icache_enable(void)