From patchwork Fri Jan 4 00:37:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 1020558 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 43W5Yn1g4Yz9s7T for ; Fri, 4 Jan 2019 11:41:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E27A0C21C50; Fri, 4 Jan 2019 00:38:39 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D54F9C21DD9; Fri, 4 Jan 2019 00:38:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3116DC21C50; Fri, 4 Jan 2019 00:38:01 +0000 (UTC) Received: from mail-edgeDD24.fraunhofer.de (mail-edgeDD24.fraunhofer.de [192.102.167.24]) by lists.denx.de (Postfix) with ESMTPS id D6794C21C2C for ; Fri, 4 Jan 2019 00:38:00 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2FbAAAO4PJb/xoBYJliGgEBAQEBAgEBAQEHAgEBAQGBZYIEgVY5jG+LHZRMhnENhGwCg24iOBIBAwEBAgEBAgICaSiFPgYyAUYQUT0aBg4FgyGCAQGofIocCQGHUIQrgVc/gRABiF2FDgKLCJRnBwKBEYEJBI5+CxiJWIclLJdqgV0igVUzGiSDO4InF44dPgEyAY5bAQE X-IPAS-Result: A2FbAAAO4PJb/xoBYJliGgEBAQEBAgEBAQEHAgEBAQGBZYIEgVY5jG+LHZRMhnENhGwCg24iOBIBAwEBAgEBAgICaSiFPgYyAUYQUT0aBg4FgyGCAQGofIocCQGHUIQrgVc/gRABiF2FDgKLCJRnBwKBEYEJBI5+CxiJWIclLJdqgV0igVUzGiSDO4InF44dPgEyAY5bAQE X-IronPort-AV: E=Sophos;i="5.56,253,1539640800"; d="scan'208";a="22609577" Received: from mail-mtaka26.fraunhofer.de ([153.96.1.26]) by mail-edgeDD24.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Jan 2019 01:37:59 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0DkAACO3/Jb/xBhWMBiGwEBAQEDAQEBBwMBAQGBZYM5ITmMb59phnENhGwChA84EgEDAQECAQECbSiFPQYyAUYQUT0aBg4FgyGCAqh2ihwJAYdQhgI/gRABiF2FDgKLCJRnBwKBEYEJBI5+CxiJWIclLJdqgV0hgVUzGiSDO4InF44dPgMwAY5bAQE X-IronPort-AV: E=Sophos;i="5.56,253,1539640800"; d="scan'208";a="25618101" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP12EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaKA26.fraunhofer.de with ESMTP/TLS/AES256-SHA; 04 Jan 2019 01:38:00 +0100 Received: from localhost.de (10.80.233.51) by FGDEMUCIMP12EXC.ads.fraunhofer.de (10.80.232.43) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 4 Jan 2019 01:38:00 +0100 From: Lukas Auer To: Date: Fri, 4 Jan 2019 01:37:29 +0100 Message-ID: <20190104003734.28052-3-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190104003734.28052-1-lukas.auer@aisec.fraunhofer.de> References: <20190104003734.28052-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24328.005 X-TM-AS-Result: No--3.857700-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Greentime Hu Subject: [U-Boot] [PATCH v2 2/7] riscv: move the AX25-specific implementation of flush_dcache_all X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The fence instruction is used to enforce device I/O and memory ordering constraints in RISC-V. It can not be relied on to directly affect the data cache on every CPU. Andes' AX25 does not have a coherence agent. Its fence instruction flushes the data cache and is used to keep data in the system coherent. The implementation of flush_dcache_all in lib/cache.c is therefore specific to the AX25. Move it into the AX25-specific cache.c in cpu/ax25/. This also adds a missing new line between flush_dcache_all and flush_dcache_range in lib/cache.c. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v2: - Replace patch "riscv: remove invalid dcache flush implementation" with new patch "riscv: move the AX25-specific implementation of flush_dcache_all" arch/riscv/cpu/ax25/cache.c | 22 ++++++++++++++++++++++ arch/riscv/lib/cache.c | 10 ++++------ 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/arch/riscv/cpu/ax25/cache.c b/arch/riscv/cpu/ax25/cache.c index 8d6ae170b8..228fc55f56 100644 --- a/arch/riscv/cpu/ax25/cache.c +++ b/arch/riscv/cpu/ax25/cache.c @@ -6,6 +6,28 @@ #include +void flush_dcache_all(void) +{ + /* + * Andes' AX25 does not have a coherence agent. U-Boot must use data + * cache flush and invalidate functions to keep data in the system + * coherent. + * The implementation of the fence instruction in the AX25 flushes the + * data cache and is used for this purpose. + */ + asm volatile ("fence" ::: "memory"); +} + +void flush_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + +void invalidate_dcache_range(unsigned long start, unsigned long end) +{ + flush_dcache_all(); +} + void icache_enable(void) { #ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index ae5c60716f..78b19da2c5 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -11,13 +11,12 @@ void invalidate_icache_all(void) asm volatile ("fence.i" ::: "memory"); } -void flush_dcache_all(void) +__weak void flush_dcache_all(void) { - asm volatile ("fence" :::"memory"); } -void flush_dcache_range(unsigned long start, unsigned long end) + +__weak void flush_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void invalidate_icache_range(unsigned long start, unsigned long end) @@ -29,9 +28,8 @@ void invalidate_icache_range(unsigned long start, unsigned long end) invalidate_icache_all(); } -void invalidate_dcache_range(unsigned long start, unsigned long end) +__weak void invalidate_dcache_range(unsigned long start, unsigned long end) { - flush_dcache_all(); } void cache_flush(void)