From patchwork Wed Dec 5 06:29:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1008021 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="XHq7YbHy"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 438pll5kRFz9s7W for ; Wed, 5 Dec 2018 17:31:15 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 85FDEC22496; Wed, 5 Dec 2018 06:30:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 14EEEC2249D; Wed, 5 Dec 2018 06:30:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2A749C224A8; Wed, 5 Dec 2018 06:29:53 +0000 (UTC) Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) by lists.denx.de (Postfix) with ESMTPS id 94254C224A8 for ; Wed, 5 Dec 2018 06:29:48 +0000 (UTC) Received: by mail-pg1-f196.google.com with SMTP id 80so8539559pge.4 for ; Tue, 04 Dec 2018 22:29:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uE/zi90w/BuqAYx5CvO05hzGhRugLrIxvk3v3SHHXqk=; b=XHq7YbHyVj6HBI+Tmc9V7qWFyRbwWgu2vbZFZK6Jhb+3Tr3THoO9d6TuMzUIA3eBYg +IVtl+/mWXymb9xxRMqCNf2vPRUkemCqGm6/ifxXyHCLQ7cpq7PtYiXyYuicFbES8W8B Jl+4P6N9JmTbMMLBnH6bvrXjpdlUFONBtXyKZoe9Bq/DuepaU+X2e3PH8+kEE/t/53J2 DIVr1L4Nrlo3V/1nhJDSDUYK4aRRA6up1NMDetuEeFcLT1yfOu8/c0D3Qm12ggvXb08Q C+ziP6nwCqX8dw5rhpuGCfDeObH3uzmZp132mAT7Clg7agSO/D3kQkp0TpI5yNAPlsTT rihg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uE/zi90w/BuqAYx5CvO05hzGhRugLrIxvk3v3SHHXqk=; b=oqEMvW5rqpmN9sSh6Mi5/CEZeHfrVdyrbD/v1916ZG/nTN9JMR9rh2mEWAM1do7QHB FAKS8g08czIJ/oxlzpc7BIn1l6+ogVbvS0VgAnvIaA3oWM8iBdNu47QjknXsGEcFMQxA 5KTYmN6R9EairC8bJrN1XT9cZeJCFV03s0nSSXEPACdlieMJSgmzGshhqhT4XNmR+OBO rNe1DE5H4f+zylSx6xUQaMxnIYROk7fPr7E+JJzsQ6bgTWAlvTIYUBGeqVx2hGDc0AhE Cf6pH298+M/j10Tn+O3V/IX9e9VV2A7YH8CfL6TGjedfcCPrbiYS7G6VWHqB6FzED7YM tt6Q== X-Gm-Message-State: AA+aEWbjzreROitrVq63ge6FYfrwqTF0UVpXHfGZeyquLS67xAmnU66e JE6nGUzN2TZdfhh49Np1iYHGvw== X-Google-Smtp-Source: AFSGD/V4Z3m/7LHhBpZj4MJwKaawRCDyxpW2/ceKW/aV2SEveYOlHKOYfN6EBpWms9Hcu+WuFB933w== X-Received: by 2002:a63:5320:: with SMTP id h32mr19457913pgb.414.1543991387088; Tue, 04 Dec 2018 22:29:47 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([49.207.50.107]) by smtp.googlemail.com with ESMTPSA id s184sm43934545pgc.38.2018.12.04.22.29.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Dec 2018 22:29:46 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Wed, 5 Dec 2018 11:59:24 +0530 Message-Id: <20181205062924.26640-3-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181205062924.26640-1-anup@brainfault.org> References: <20181205062924.26640-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH 2/2] riscv: qemu: Enable SiFive UART driver in defconfigs X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch enables SiFive UART driver in all QEMU RISC-V defconfigs. Signed-off-by: Anup Patel Reviewed-by: Palmer Dabbelt --- configs/qemu-riscv32_defconfig | 1 + configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv64_defconfig | 1 + configs/qemu-riscv64_smode_defconfig | 1 + 4 files changed, 4 insertions(+) diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 6334d8c0fc..79c8d54cc7 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -7,3 +7,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index 0a84ec1874..b733dbed2f 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -8,3 +8,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig index 2d9ead93a2..a9d19a5574 100644 --- a/configs/qemu-riscv64_defconfig +++ b/configs/qemu-riscv64_defconfig @@ -8,3 +8,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig index b012443370..8adc23f826 100644 --- a/configs/qemu-riscv64_smode_defconfig +++ b/configs/qemu-riscv64_smode_defconfig @@ -9,3 +9,4 @@ CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y # CONFIG_CMD_MII is not set CONFIG_OF_PRIOR_STAGE=y +CONFIG_SIFIVE_SERIAL=y