From patchwork Mon Dec 3 05:27:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1006663 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="IcsrnNZe"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 437YVW3Hpwz9sBh for ; Mon, 3 Dec 2018 16:30:27 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2CD34C226DB; Mon, 3 Dec 2018 05:29:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A9879C220BC; Mon, 3 Dec 2018 05:28:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 44D74C22086; Mon, 3 Dec 2018 05:28:20 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id 3A422C22680 for ; Mon, 3 Dec 2018 05:28:16 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id a14so5837076plm.12 for ; Sun, 02 Dec 2018 21:28:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=odk1I7L00udgfJ156E3htvHMQ0x8XkgAxbQD4I+VAPE=; b=IcsrnNZeXgxjnacb7Z5GpQq7a0TtdOmkRMShlAWbCa3qTp7ra7d8bXqLWWk5MH0LYD ZwtYeWzyAxJGTzfd3yux3YjWYZbyMQgPoyR2Mcapv5pWOM620xF5RZXWKscxIRov3xWb 2UbxVKK9JPzVQhM3ctTgouWFaDdCwjvYYdNHKPms8mstZeDYvq2KPGIARani0gQGmylQ QbiBjvL2dj62hPZgStsOTKCDMEpbpVeRKguhcAwG7CUHtJyAMxZ0WNxbzaiD9tQsyeM4 vRFwcLhsy9Png9ZvvfGo0fA8a6qiHllIZ7tqOggX5oX57xerlV+P2IYk6Y2wpzz9eiHS 3kbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=odk1I7L00udgfJ156E3htvHMQ0x8XkgAxbQD4I+VAPE=; b=Qi+aRtUjLEg3B5dqqT2bfraTedPuQvwiymyGg9az3t56SxB7xzQDqJ3ZS/v0gUu+r0 WPjkHxefLG68pllnVNXJOdQJ2XxCvMpfifrOJi6f9lETDUMyvwlPkgz0967qw9TcF8uX 3s7q9eZlqZWDNc5xgO4YjDiISDmA844brXO+Hx2/7Z+/JJU0dpy/iKOmAZCTTK04iV4Z qn54a4i4xsJz905zrJygrHMi9PcS1DuuNPENjp/MnK/fS456nK+JuVMjFQj90xLnVGwH ppXJDp72O0gFYvW5iVGjonZAW8+AG3v5qiDZX5460jI0VIeM3w5d6u9NWK18u1e7ZtdX BOfA== X-Gm-Message-State: AA+aEWZ9Cp7z4BDW+W+eR9ZnzJzCYchcjFW15ixXb6kjJ0ZjiihQE+iU TjxJUswgFQwYekROTAGKy6ck8A== X-Google-Smtp-Source: AFSGD/WNcyQi0RZifPg1sP0BdTG5Ld2VenS5Toa7WygRWJi3msAxMY1zocknY6pBXD09ZxQ0YYColQ== X-Received: by 2002:a17:902:7c82:: with SMTP id y2mr14402441pll.33.1543814894616; Sun, 02 Dec 2018 21:28:14 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([106.51.23.39]) by smtp.googlemail.com with ESMTPSA id n22sm28711233pfh.166.2018.12.02.21.28.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Dec 2018 21:28:14 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Mon, 3 Dec 2018 10:57:43 +0530 Message-Id: <20181203052743.29036-5-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181203052743.29036-1-anup@brainfault.org> References: <20181203052743.29036-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v7 4/4] RISC-V: Add S-mode timer implementation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When running in S-mode, we can use rdtime and rdtimeh instructions for reading timer ticks (just like Linux). The frequency of timer ticks is passed by prior booting stages in "timebase-frequency" DT property of the "/cpus" DT node. This patch provides a generic timer implementation for U-Boot running in S-mode. For U-Boot running in M-mode, specific timer drivers will have to be provided. Signed-off-by: Anup Patel --- arch/Kconfig | 1 - arch/riscv/Kconfig | 22 +++++++++++---- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/time.c | 60 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 78 insertions(+), 6 deletions(-) create mode 100644 arch/riscv/lib/time.c diff --git a/arch/Kconfig b/arch/Kconfig index 9fdd2f7e66..a4fcb3522d 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -72,7 +72,6 @@ config RISCV imply BLK imply CLK imply MTD - imply TIMER imply CMD_DM config SANDBOX diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 732a357a99..20a060454b 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -44,6 +44,23 @@ config ARCH_RV64I endchoice +choice + prompt "Run Mode" + default RISCV_MMODE + +config RISCV_MMODE + bool "Machine" + select TIMER + help + Choose this option to build U-Boot for RISC-V M-Mode. + +config RISCV_SMODE + bool "Supervisor" + help + Choose this option to build U-Boot for RISC-V S-Mode. + +endchoice + config RISCV_ISA_C bool "Emit compressed instructions" default y @@ -55,11 +72,6 @@ config RISCV_ISA_C config RISCV_ISA_A def_bool y -config RISCV_SMODE - bool "Run in S-Mode" - help - Enable this option to build U-Boot for RISC-V S-Mode - config 32BIT bool diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index b58db89752..98aa6d40e7 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -12,6 +12,7 @@ obj-y += cache.o obj-y += interrupts.o obj-y += reset.o obj-y += setjmp.o +obj-$(CONFIG_RISCV_SMODE) += time.o # For building EFI apps CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI) diff --git a/arch/riscv/lib/time.c b/arch/riscv/lib/time.c new file mode 100644 index 0000000000..077e568ca6 --- /dev/null +++ b/arch/riscv/lib/time.c @@ -0,0 +1,60 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018, Anup Patel + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned int tbclk; + +static void setup_tbclk(void) +{ + int cpus; + + if (!gd->fdt_blob || tbclk) + return; + + cpus = fdt_path_offset(gd->fdt_blob, "/cpus"); + if (cpus < 0) { + debug("%s: Missing /cpus node\n", __func__); + return; + } + + tbclk = fdtdec_get_int(gd->fdt_blob, cpus, + "timebase-frequency", 1000000); +} + +ulong notrace get_tbclk(void) +{ + setup_tbclk(); + + return tbclk; +} + +#ifdef CONFIG_64BIT +uint64_t notrace get_ticks(void) +{ + unsigned long n; + + __asm__ __volatile__ ( + "rdtime %0" + : "=r" (n)); + return n; +} +#else +uint64_t notrace get_ticks(void) +{ + uint32_t lo, hi, tmp; + __asm__ __volatile__ ( + "1:\n" + "rdtimeh %0\n" + "rdtime %1\n" + "rdtimeh %2\n" + "bne %0, %2, 1b" + : "=&r" (hi), "=&r" (lo), "=&r" (tmp)); + return ((uint64_t)hi << 32) | lo; +} +#endif