From patchwork Mon Dec 3 05:27:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1006662 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="WaeAXGp4"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 437YTl43bNz9s3Z for ; Mon, 3 Dec 2018 16:29:47 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 343BDC22074; Mon, 3 Dec 2018 05:28:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 84AC8C21FEF; Mon, 3 Dec 2018 05:28:24 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5A606C220BC; Mon, 3 Dec 2018 05:28:11 +0000 (UTC) Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) by lists.denx.de (Postfix) with ESMTPS id 66C5DC21FF7 for ; Mon, 3 Dec 2018 05:28:07 +0000 (UTC) Received: by mail-pf1-f195.google.com with SMTP id w73so5756372pfk.10 for ; Sun, 02 Dec 2018 21:28:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cKbxcUi8EFtXRX6ZKTRteFrEA1MNrvc3hL5H4tJKH1Y=; b=WaeAXGp4Mp/M6nTbYAH90ENOEe97rJKo8XGHQpljd69LPkFQCSSmi3Eh7A2fhhoxg9 hWM2ElZH5nkIji59GDJSqTVi0frmET+orVvajXUspKSMe0spdPuct6T0WnvUUoD2P5UD NX3VU5s2Fo1qQkjT1WxZGxPlc2O7kXRwZTZyXWIH4UJfHAlYEPc03yloxcIn8vu/wOsS Fqip6G2Ee/Akgera25imz8y3jYoty0Eq1e54FFnn7sZODeCr+sfG1xUdWX5yFfIPMdd3 aYEBlH4XPEHGmEpjibNH62lzY6ept+Ir6qMn+WwGfbmysY7LqHrHh/XuV/xPTTXr9O0N 4pUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cKbxcUi8EFtXRX6ZKTRteFrEA1MNrvc3hL5H4tJKH1Y=; b=jfIwruwcELMNcAwhDUH5OQzgBB2VQP1asu/PNpDhSjiTpFWUjehfS9zcNZ47pFy/T7 0WRHedQniaiNBDU4TXCxH58yeWTkCKQhPUH2r4q9p16umRMEcf2l6WC/1GNhXTndCVvH XZqXgtSQhdAdduOSy+Mno4Bls6WgbQ7FRaT5t0+RMHxgWXaZzRn0R2Ik86qlKmcTR/rS atTkmC04KBFYHk0Wmu0MxGNHLTJmE+zkOwVV+N1rpMarIfhXepJdIflFh+68vDY4WCby rDE5ANWz6d0EHEer+aK+m5spYLttNP3UUkydQlTWv4x4TXUsgseVbpvSZx7MjOb8lUCo 0i+w== X-Gm-Message-State: AA+aEWY/9gxOY+FVhK8pDnE3/iCyAU12dhGia9QhVnHhh7buqdPQWSQb cJ6pt4QwoOtwhemqz9WUdE0vmA== X-Google-Smtp-Source: AFSGD/VtW8RVsfsq5iPFNah6tZ6TI9PI7zpjPz3TZTf5vIcmZVpaezXYq9SMwrt/9QC0apMOsMpKbg== X-Received: by 2002:a62:5ec5:: with SMTP id s188mr14248907pfb.145.1543814885824; Sun, 02 Dec 2018 21:28:05 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([106.51.23.39]) by smtp.googlemail.com with ESMTPSA id n22sm28711233pfh.166.2018.12.02.21.28.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Dec 2018 21:28:05 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Mon, 3 Dec 2018 10:57:41 +0530 Message-Id: <20181203052743.29036-3-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181203052743.29036-1-anup@brainfault.org> References: <20181203052743.29036-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v7 2/4] riscv: qemu: Use different SYS_TEXT_BASE for S-mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When u-boot runs in S-mode, the M-mode runtime firmware (BBL or equivalent) uses memory range in 0x80000000 to 0x80200000. Due to this, we cannot use 0x80000000 as SYS_TEXT_BASE when running in S-mode. Instead for S-mode, we use 0x80200000 as SYS_TEXT_BASE. Even Linux RISC-V kernel ignores/reserves memory range 0x80000000 to 0x80200000 because it runs in S-mode. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Lukas Auer --- board/emulation/qemu-riscv/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 33ca253432..56bb5337d4 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -13,7 +13,8 @@ config SYS_CONFIG_NAME default "qemu-riscv" config SYS_TEXT_BASE - default 0x80000000 + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y