From patchwork Mon Dec 3 05:27:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1006660 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="CPFNvMwU"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 437YSz2Zxlz9s3Z for ; Mon, 3 Dec 2018 16:29:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 05DEAC2201E; Mon, 3 Dec 2018 05:28:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C1FC3C22691; Mon, 3 Dec 2018 05:28:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C162CC22685; Mon, 3 Dec 2018 05:28:07 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id B6F3BC22086 for ; Mon, 3 Dec 2018 05:28:02 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id e5so5852276plb.5 for ; Sun, 02 Dec 2018 21:28:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=18QrhhAgnziZ/rQVrwBMVjCL5MAiBseC9VBMZ9qU45c=; b=CPFNvMwU02njG/P9o+z0ETzG9lxTjk2b40N3SOLc7za1tnDYjmDeu17uC5XqzkL5q8 DIqaufvOEcgCHs/B2+/iH20drzSzXrsVKkfMie7hp5x9w5vWY8n1hU1rR9YvQIJZ0Bep DdOUq5zGDK5WwUQlp+3FordtJl1DLkELnIOwKJRf9fuIHq5q88LvXJ43mIzZnH0nhG8U cNYOc9b9YhFe6fcRbHRv3grp8ox6QXLCGxsntPdYy2Sj4b2vY5R3ZNjULSYmHB/8uytN FA3iOx5UuHT5WE6u9w8eSvBOaUBKWQVeyMoM/8/FMJxjXluFjY531vzXU4dsDmFag4Pn UXgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=18QrhhAgnziZ/rQVrwBMVjCL5MAiBseC9VBMZ9qU45c=; b=mo9ub73Z0gOGDRmbeuE+xTKB+MNxEzdUeq1KaiDXncX3bt6a6NZa/ynLS9NXdT5WBg t+OJ9HXFO95stbc5rawTznuPBza6ANIksoB/ez5Kzrzg3yP0gwALe+6S9JKm89KF5A39 RicCPaxXwEzAcBk6n0GsdaaS4IE8w9te5QE67/VUYx4WydIzX1eah1YM2RdOW7A0yDuE UIgrvJAO0Yw1FhfbFwCL13iGYe/ANaG9q+p2sAnyQpKL9t6XmZQHPfRzAMkJ8G2CJ7W5 gKqRcC6hSNvpxlGPMO3aj7Vi+3zpbFLtsff6qHZmj0WR/MkK4/3guxUUfnOgqUP3UgIa kqWg== X-Gm-Message-State: AA+aEWawcC9IZN7zNNcQr2iJCMehHZjSd9DcThDEg7bfAFIyH6oUX7HP eZcZ7rzRuPoZ6+X0n1baUyorQg== X-Google-Smtp-Source: AFSGD/VKkvKRA7/2LrwvLTxKqFwV0f41hJvornuCEqPP6x3tLA+5azZl0tIYh3g9LiF6VovWPwuG6w== X-Received: by 2002:a17:902:2ac3:: with SMTP id j61mr14616687plb.185.1543814881196; Sun, 02 Dec 2018 21:28:01 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([106.51.23.39]) by smtp.googlemail.com with ESMTPSA id n22sm28711233pfh.166.2018.12.02.21.27.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Dec 2018 21:28:00 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Mon, 3 Dec 2018 10:57:40 +0530 Message-Id: <20181203052743.29036-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181203052743.29036-1-anup@brainfault.org> References: <20181203052743.29036-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v7 1/4] riscv: Add kconfig option to run U-Boot in S-mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s CSRs instead of m CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/Kconfig | 5 +++++ arch/riscv/cpu/start.S | 23 +++++++++++++++-------- arch/riscv/include/asm/encoding.h | 6 ++++++ arch/riscv/lib/interrupts.c | 31 ++++++++++++++++++++++--------- 4 files changed, 48 insertions(+), 17 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3e0af55e71..732a357a99 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -55,6 +55,11 @@ config RISCV_ISA_C config RISCV_ISA_A def_bool y +config RISCV_SMODE + bool "Run in S-Mode" + help + Enable this option to build U-Boot for RISC-V S-Mode + config 32BIT bool diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 15e1b8199a..3f055bdb7e 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -41,10 +41,10 @@ _start: li t0, CONFIG_SYS_SDRAM_BASE SREG a2, 0(t0) la t0, trap_entry - csrw mtvec, t0 + csrw MODE_PREFIX(tvec), t0 /* mask all interrupts */ - csrw mie, zero + csrw MODE_PREFIX(ie), zero /* Enable cache */ jal icache_enable @@ -166,7 +166,7 @@ fix_rela_dyn: */ la t0, trap_entry add t0, t0, t6 - csrw mtvec, t0 + csrw MODE_PREFIX(tvec), t0 clear_bss: la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ @@ -238,17 +238,24 @@ trap_entry: SREG x29, 29*REGBYTES(sp) SREG x30, 30*REGBYTES(sp) SREG x31, 31*REGBYTES(sp) - csrr a0, mcause - csrr a1, mepc + csrr a0, MODE_PREFIX(cause) + csrr a1, MODE_PREFIX(epc) mv a2, sp jal handle_trap - csrw mepc, a0 + csrw MODE_PREFIX(epc), a0 +#ifdef CONFIG_RISCV_SMODE +/* + * Remain in S-mode after sret + */ + li t0, SSTATUS_SPP +#else /* * Remain in M-mode after mret */ li t0, MSTATUS_MPP - csrs mstatus, t0 +#endif + csrs MODE_PREFIX(status), t0 LREG x1, 1*REGBYTES(sp) LREG x2, 2*REGBYTES(sp) LREG x3, 3*REGBYTES(sp) @@ -281,4 +288,4 @@ trap_entry: LREG x30, 30*REGBYTES(sp) LREG x31, 31*REGBYTES(sp) addi sp, sp, 32*REGBYTES - mret + MODE_PREFIX(ret) diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 9ea50ce640..97cf906aa6 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -7,6 +7,12 @@ #ifndef RISCV_CSR_ENCODING_H #define RISCV_CSR_ENCODING_H +#ifdef CONFIG_RISCV_SMODE +#define MODE_PREFIX(__suffix) s##__suffix +#else +#define MODE_PREFIX(__suffix) m##__suffix +#endif + #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 #define MSTATUS_HIE 0x00000004 diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 903a1c4cd5..3aff006977 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -34,17 +34,30 @@ int disable_interrupts(void) return 0; } -ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs) +ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs) { - ulong is_int; + ulong is_irq, irq; - is_int = (mcause & MCAUSE_INT); - if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) - external_interrupt(0); /* handle_m_ext_interrupt */ - else if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) - timer_interrupt(0); /* handle_m_timer_interrupt */ - else - _exit_trap(mcause, epc, regs); + is_irq = (cause & MCAUSE_INT); + irq = (cause & ~MCAUSE_INT); + + if (is_irq) { + switch (irq) { + case IRQ_M_EXT: + case IRQ_S_EXT: + external_interrupt(0); /* handle external interrupt */ + break; + case IRQ_M_TIMER: + case IRQ_S_TIMER: + timer_interrupt(0); /* handle timer interrupt */ + break; + default: + _exit_trap(cause, epc, regs); + break; + }; + } else { + _exit_trap(cause, epc, regs); + } return epc; }