From patchwork Mon Dec 3 05:27:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1006659 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="bT8V7RBN"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 437YRs5WqWz9sBh for ; Mon, 3 Dec 2018 16:28:09 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6921BC22665; Mon, 3 Dec 2018 05:28:02 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 11584C21F77; Mon, 3 Dec 2018 05:28:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A92A2C21F77; Mon, 3 Dec 2018 05:27:58 +0000 (UTC) Received: from mail-pl1-f194.google.com (mail-pl1-f194.google.com [209.85.214.194]) by lists.denx.de (Postfix) with ESMTPS id 04301C21EE4 for ; Mon, 3 Dec 2018 05:27:58 +0000 (UTC) Received: by mail-pl1-f194.google.com with SMTP id 101so5847452pld.6 for ; Sun, 02 Dec 2018 21:27:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=O0UpdSqTICN/UgNJ5B8FU7b16aCeK/yKxIZHxjZ9Cac=; b=bT8V7RBNCzLqExtPipzp3Q8ir0dEsVJbq1J0OghM566KguyXNLJUYnZVY3rjCPjhuU kiYak2jO+iHaj+FbrF1kmX3OfuFsUrydH0ESw07xp9p2GgVs1qhg/pLmPr75p5co6Ae6 9XmzQIYsUpa1png4Vvvzd5n0qSkwiTQJQzZHXJTBd8qRuHIMO0WEgFXSb6EhhFX3ffHH MJEtNmC1XyYMW70FoAhc68tFAa95o1McU1ANx67ABbiZZV0mRZFIIYlyUAOjCL6sRkMe lDezHg2t+JwPzCn/b40US9Xvyr+Famz2HDEa2/T5ecchaJ/xfNs30LXI1jyVZuvuu0yf f+Vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=O0UpdSqTICN/UgNJ5B8FU7b16aCeK/yKxIZHxjZ9Cac=; b=oWEduZbk86OwAP9ed0O3sDr0djH89F3uUxy4iOy15/qrIQy6+VdPV5GloeqyD4lVWD G81ksJkCjNaC7Z+mS4oOqMgv+VH7D9doedgKySZe6RI3XZuCGWiykRVNcryw6a5dfUr7 Suktx5r4c+xA7VpJyUZvsZ+D20YGYgR1zTske07l6o1I+8T5uLA9KxCjuQ/fkoSdUs5z +PESMASQ9Ttmk21s3wFIxSAxLNFtvJS35Xe/fJpWcdp6RmVYRhHQkWvweF3gUZ0mQLuU 7ptxmaM7NJGGO7MamvRUokl37aOkp/Q8Tgzom/vx57/ZsJ/MMg7jwoXmfmJgEbhY9+E9 4T0A== X-Gm-Message-State: AA+aEWaNzM/psIWgDeI6g8VxZhWqlBsBAK8txo9/UUm2BUTjHXwx0alE CVhTnL+qdikljkvF3EBPUB/8rw== X-Google-Smtp-Source: AFSGD/Whn4ZET/7JPF+QgoeTqP5cBa6nJhgrP1vtGC8xw+keZCJ4bLLcT49uM7pvCadBjypWXeMBZw== X-Received: by 2002:a17:902:7b91:: with SMTP id w17mr14652043pll.111.1543814876116; Sun, 02 Dec 2018 21:27:56 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([106.51.23.39]) by smtp.googlemail.com with ESMTPSA id n22sm28711233pfh.166.2018.12.02.21.27.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 02 Dec 2018 21:27:55 -0800 (PST) From: Anup Patel To: Rick Chen , Bin Meng , Lukas Auer Date: Mon, 3 Dec 2018 10:57:39 +0530 Message-Id: <20181203052743.29036-1-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v7 0/4] RISC-V S-mode support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patchset allows us runing u-boot in S-mode which is useful on platforms where M-mode runtime firmware is an independent firmware and u-boot is used as last stage OS bootloader. The patchset based upon git://git.denx.de/u-boot-riscv.git and is tested on QEMU in both M-mode and S-mode. For S-mode testing, we have used u-boot.bin as payload of latest BBL (at commit 6ebd0f2a46255d0c76dad3c05b16c1d154795d26) applied with following changes: Changes since v6: - Added patch for S-mode timer implementation Changes since v5: - Dropped PATCH4 to remove redundant a2 store on DRAM base in start.S because it will taken care by Rick as separate patch - Added MODE_PREFIX() macro to generate mode specific CSR names Changes since v4: - Rebased series based on commit 52923c6db7f00e0197ec894c8c1bb8a7681974bb of git://git.denx.de/u-boot-riscv.git - Added a patch to remove redundant a2 store on DRAM base. This store was creating problem booting U-Boot in S-mode using BBL. Changes since v3: - Replaced 'u-boot' with 'U-Boot' in commit message - Dropped 'an' in RISCV_SMODE kconfig option help message - Added appropriate #ifdef in arch/riscv/lib/interrupts.c Changes since v2: - Dropped 'default n" from RISCV_SMODE kconfig option - Replaced '-smode_' in defconfig names with '_smode_' Changes since v1: - Rebased upon latest git://git.denx.de/u-boot-riscv.git - Add details in cover letter for running u-boot in S-mode using BBL Anup Patel (4): riscv: Add kconfig option to run U-Boot in S-mode riscv: qemu: Use different SYS_TEXT_BASE for S-mode riscv: Add S-mode defconfigs for QEMU virt machine RISC-V: Add S-mode timer implementation arch/Kconfig | 1 - arch/riscv/Kconfig | 17 ++++++++ arch/riscv/cpu/start.S | 23 ++++++---- arch/riscv/include/asm/encoding.h | 6 +++ arch/riscv/lib/Makefile | 1 + arch/riscv/lib/interrupts.c | 31 +++++++++---- arch/riscv/lib/time.c | 60 ++++++++++++++++++++++++++ board/emulation/qemu-riscv/Kconfig | 3 +- board/emulation/qemu-riscv/MAINTAINERS | 2 + configs/qemu-riscv32_smode_defconfig | 10 +++++ configs/qemu-riscv64_smode_defconfig | 11 +++++ 11 files changed, 146 insertions(+), 19 deletions(-) create mode 100644 arch/riscv/lib/time.c create mode 100644 configs/qemu-riscv32_smode_defconfig create mode 100644 configs/qemu-riscv64_smode_defconfig diff --git a/machine/emulation.c b/machine/emulation.c index 132e977..def75e1 100644 --- a/machine/emulation.c +++ b/machine/emulation.c @@ -162,6 +162,12 @@ static inline int emulate_read_csr(int num, uintptr_t mstatus, uintptr_t* result switch (num) { + case CSR_MISA: + *result = read_csr(misa); + return 0; + case CSR_MHARTID: + *result = read_csr(mhartid); + return 0; case CSR_CYCLE: if (!((counteren >> (CSR_CYCLE - CSR_CYCLE)) & 1)) return -1;