From patchwork Fri Nov 30 11:36:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1005897 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="gfd8MhoC"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 435snF3V0fz9s9m for ; Fri, 30 Nov 2018 22:37:17 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0D5A7C2242B; Fri, 30 Nov 2018 11:37:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 572BAC21EFB; Fri, 30 Nov 2018 11:37:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 00F99C21EFB; Fri, 30 Nov 2018 11:37:06 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id 68F67C21EC8 for ; Fri, 30 Nov 2018 11:37:06 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id b5so2685990plr.4 for ; Fri, 30 Nov 2018 03:37:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=nMAfGkL7IoHFhDjC1HP/g7FA0ohP1gBFRK8ECz5qqNo=; b=gfd8MhoCuVuGwkQvtkth/ZB9V1idciyFLx3qv6aXxB9Zn9I39Bdrf6RbsM6LcZRF2j XXJg5bEsIfB8JBOzjA9kKvdYESMsHiSA27cAmoYCsDkVqbc8LMCKqpKd0gWJbTY+uqDR mlRcT6iPLLcFeubT7IsktyUDqiKBHK8QJz4+nIW8pW4nMQ/VlHqC834q/iwkkpHLbdfB aWYH33/ZKehH9qDqk8+ATox8wbHAhzXAZoISXS1UdkWYaSELe4Qx//L0ZP/zektNsdw4 q/YFhR2mRb0MMF3qcd+xZzGSC3JjkZoNowH1BtVQ6X7yytkGiArMij+GInV7ZbsJ5sVy 1yQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=nMAfGkL7IoHFhDjC1HP/g7FA0ohP1gBFRK8ECz5qqNo=; b=kWg/T9zqsLCCRPQnz5eR+pKW9hl5H+CHLq3tl68v6nOSYetSO/Idb8aUO0I8uPD1tq 8ZnHJZI2sAI1JtuxTQ7ftwoDgMoWlUcaFdJzjPTKHO9yKF5T2mzFC/C2bq+SIpV/sW9e 4uDrGKG1PtEbcp2SNzO7LaF7alKQdiMldBo736hhZoqMuifTEtMW/aKv2iN5yh/Cb8F4 oSLlU1NMiTGNi5xil09G5Mo7BisRJkFr77fK9m6FuQu098nN69R8Q9bWWRGTi75VivoI n5qYtE00Sq2ijolIBeYaEiWNh4H/b5k3azP5LZ2qkRrSdCiVa/AQw94ZR2ihr3x/zPFH rttw== X-Gm-Message-State: AA+aEWZr7C2FNgnPWUp3WTq1a0Hoydg2x9jLqP5MqMXpVzki6ZxAUVeP kLYZFzm1wUmXGl70G3T0frMioA== X-Google-Smtp-Source: AFSGD/UqFXcS+qy7dtUkfjyR0Vl786gSCf75fhopb6jHW9S/JuSC6L1KD5iBnyj7CbFL7ka5X4DWOg== X-Received: by 2002:a17:902:4222:: with SMTP id g31mr5316774pld.240.1543577824638; Fri, 30 Nov 2018 03:37:04 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([49.207.52.208]) by smtp.googlemail.com with ESMTPSA id g15sm23603506pfj.131.2018.11.30.03.37.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Nov 2018 03:37:03 -0800 (PST) From: Anup Patel To: Rick Chen Date: Fri, 30 Nov 2018 17:06:49 +0530 Message-Id: <20181130113652.7157-1-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v6 0/3] RISC-V S-mode support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patchset allows us runing u-boot in S-mode which is useful on platforms where M-mode runtime firmware is an independent firmware and u-boot is used as last stage OS bootloader. The patchset based upon git://git.denx.de/u-boot-riscv.git and is tested on QEMU in both M-mode and S-mode. For S-mode testing, we have used u-boot.bin as payload of latest BBL (at commit 6ebd0f2a46255d0c76dad3c05b16c1d154795d26) applied with following changes: Changes since v5: - Dropped PATCH4 to remove redundant a2 store on DRAM base in start.S because it will taken care by Rick as separate patch - Added MODE_PREFIX() macro to generate mode specific CSR names Changes since v4: - Rebased series based on commit 52923c6db7f00e0197ec894c8c1bb8a7681974bb of git://git.denx.de/u-boot-riscv.git - Added a patch to remove redundant a2 store on DRAM base. This store was creating problem booting U-Boot in S-mode using BBL. Changes since v3: - Replaced 'u-boot' with 'U-Boot' in commit message - Dropped 'an' in RISCV_SMODE kconfig option help message - Added appropriate #ifdef in arch/riscv/lib/interrupts.c Changes since v2: - Dropped 'default n" from RISCV_SMODE kconfig option - Replaced '-smode_' in defconfig names with '_smode_' Changes since v1: - Rebased upon latest git://git.denx.de/u-boot-riscv.git - Add details in cover letter for running u-boot in S-mode using BBL Anup Patel (3): riscv: Add kconfig option to run U-Boot in S-mode riscv: qemu: Use different SYS_TEXT_BASE for S-mode riscv: Add S-mode defconfigs for QEMU virt machine arch/riscv/Kconfig | 5 +++++ arch/riscv/cpu/start.S | 23 ++++++++++++------- arch/riscv/include/asm/encoding.h | 6 +++++ arch/riscv/lib/interrupts.c | 31 ++++++++++++++++++-------- board/emulation/qemu-riscv/Kconfig | 3 ++- board/emulation/qemu-riscv/MAINTAINERS | 2 ++ configs/qemu-riscv32_smode_defconfig | 10 +++++++++ configs/qemu-riscv64_smode_defconfig | 11 +++++++++ 8 files changed, 73 insertions(+), 18 deletions(-) create mode 100644 configs/qemu-riscv32_smode_defconfig create mode 100644 configs/qemu-riscv64_smode_defconfig diff --git a/machine/emulation.c b/machine/emulation.c index 132e977..def75e1 100644 --- a/machine/emulation.c +++ b/machine/emulation.c @@ -162,6 +162,12 @@ static inline int emulate_read_csr(int num, uintptr_t mstatus, uintptr_t* result switch (num) { + case CSR_MISA: + *result = read_csr(misa); + return 0; + case CSR_MHARTID: + *result = read_csr(mhartid); + return 0; case CSR_CYCLE: if (!((counteren >> (CSR_CYCLE - CSR_CYCLE)) & 1)) return -1;