From patchwork Mon Nov 26 10:39:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1003122 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="thJ8P5bu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 433Nqz50jsz9s8F for ; Mon, 26 Nov 2018 21:46:07 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3CD63C2221A; Mon, 26 Nov 2018 10:44:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8343BC2212F; Mon, 26 Nov 2018 10:44:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E258AC22210; Mon, 26 Nov 2018 10:43:48 +0000 (UTC) Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) by lists.denx.de (Postfix) with ESMTPS id 19CC9C21FD9 for ; Mon, 26 Nov 2018 10:43:44 +0000 (UTC) Received: by mail-pg1-f196.google.com with SMTP id v28so5978018pgk.10 for ; Mon, 26 Nov 2018 02:43:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AtSVjjlY8Au5TFnnBabip+XFXYOtA4m+OTaU7GKF5SM=; b=thJ8P5bu9OpRfP5Eng1zMrpL7x4IQQChVsqDHY6WgWYzTkf4BEBUVx+DDgIGM7ZDn9 JwrBIoufBNBQ18N7BPaaoxhjZR1l+7dCqqOUt83cWNVE/+domABU1iJLKb9mPQygKzeB KlI0SNkz4yTqKK772v9TlMn+cRmPXJ5PG0f5bbKMkW3tMlmxBpIE4fDVrbbY10s4NACu SjZn/C7QP752OcBy2WMU2hH0c2d644L+Zqb9MgBuTV9ZoFd8dAXGk1n1G8UduOYzX5iV 7pXcgYgk9SmZn4YqOrO0jugsUyTBg7VQXJjm2LykB+usYBsE35Mgwkv4dcDD1+CDbm0J Wkdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AtSVjjlY8Au5TFnnBabip+XFXYOtA4m+OTaU7GKF5SM=; b=W4BlW0V2RHiBqC6Kuo5wOZnBp0dj7tSDQWO98u26fSMX4gyiKqvB9jmID1b97WSABT VaSWtkm41b8oBuZ8lziFJxYrOGD2KdlgR57x/4/ZHm/t78Of63jJYFktRY+yP8SAGzRa BLC29sH8YgMfvbVYYMrfBHkbQm/yCJjNMugw+PU1cRvfw3yvAFjlrHNBs/rQviXF+/8g P+XykLFT0GZKarm+vzw4wWNzmOIo97XIKEsmfeG+WSye3PSQBpvWYUv1FG9mca9WpKp0 TEr/+c4TNRZSGo7gfo8VrfCNCAi/70caggVZbhjcJXxDGLHzdOkLz9+G5QGVqJ0KuXPB p7lQ== X-Gm-Message-State: AA+aEWY0UIL9oDzA47dkoxo+nDG6zRlfZdzsSa4tUlpf6WTptvLjtusE QY9bRguPHNnl5cdTT+HNM/U7vw== X-Google-Smtp-Source: AFSGD/V6gmjQ9is07npn0i8qOZx6Sshl5drm/YHxSfgy81whpH+a83n+4AxNqSj1ua+daT4FnZZnfw== X-Received: by 2002:a63:cf56:: with SMTP id b22mr22999337pgj.336.1543229022615; Mon, 26 Nov 2018 02:43:42 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([49.207.53.74]) by smtp.googlemail.com with ESMTPSA id x125-v6sm9627186pfx.38.2018.11.26.02.43.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Nov 2018 02:43:41 -0800 (PST) From: Anup Patel To: Rick Chen Date: Mon, 26 Nov 2018 16:09:10 +0530 Message-Id: <20181126103910.14457-5-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181126103910.14457-1-anup@brainfault.org> References: <20181126103910.14457-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v5 4/4] riscv: Remove redundant a2 store on DRAM base in start.S X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Currently, the RISC-V U-Boot is saving a2 register at CONFIG_SYS_DRAM_BASE in start.S which does not make sense because there is no information passed by previous booting stage in a2 register. This patch removes redundant a2 store on DRAM base. Signed-off-by: Anup Patel --- arch/riscv/cpu/start.S | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 704190f946..e4276e8e19 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -38,8 +38,6 @@ _start: mv s0, a0 mv s1, a1 - li t0, CONFIG_SYS_SDRAM_BASE - SREG a2, 0(t0) la t0, trap_entry #ifdef CONFIG_RISCV_SMODE csrw stvec, t0