From patchwork Mon Nov 26 10:39:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1003118 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="2TrLAgrE"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 433Nn41h0Rz9s5c for ; Mon, 26 Nov 2018 21:43:36 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id ED6D0C21FD9; Mon, 26 Nov 2018 10:43:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4F059C21ECC; Mon, 26 Nov 2018 10:43:28 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 89218C21ECC; Mon, 26 Nov 2018 10:43:26 +0000 (UTC) Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) by lists.denx.de (Postfix) with ESMTPS id 34ED6C21DF9 for ; Mon, 26 Nov 2018 10:43:25 +0000 (UTC) Received: by mail-pg1-f195.google.com with SMTP id 17so5995809pgg.1 for ; Mon, 26 Nov 2018 02:43:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=BVRIR4zrHYK+1muH0GvCbFFuHFnlYTXbGauZhwNtsWs=; b=2TrLAgrEc474UWPtT9PS0gSvIYlfUPtL/I0yAIEXz1WImuTV8Czohxm9pKmgIMcg/Z 5I2tN48Vq1CLUTMxqFdSbY4uBsR3LPWn6IMwS2KSR3ld/per1bugd6p2SAkRw6Dg31+V H/jAvL5IUHy14cKW9k7AIEr4OLsphl6xwSELTDF2cKxosfw0FlEwtPkY43UsU3G4gTXc kXJO4s7BK1XlRVKhHa7vq6cBFEebfxS2Jom5LaxKI6Jg/Nfu0AmleuBbMgllqp6Qp6PP RkHhGuDJcTTcJ4TVGlGxVPyEzwgqpYsbkghIZJAm+M1buRprtTEBH298Dd1bi2W8IjXX 5NSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=BVRIR4zrHYK+1muH0GvCbFFuHFnlYTXbGauZhwNtsWs=; b=BV/7vuvE46zYYb2EA3071jNMzPfAGNOdpXBjBFn8T0G9unLJWsWkE2yqRJsrJPxqhw /KQVoypl71Kl+QknHDOXVbjUH0Byj43MRokvradn4yUtGmRqtgc3Ab9/JrzlzsByua4Q A1dadznJvh2D/j9EA+j9U3v0w0ogbzSoUos8yn7BUmU0ayVHrdRawH/UELOiXNU3F52v joOEUFTKpa5dsfI+tLVN8D47CGszhc3dXew4NjnVnBJp8II9oUJm/ol1SJUadtDKQ9u4 t16gE0qKc6pusewJ4LhWzslngwedfMJGOrrNwcEF2YfNM1F/+AWN61euqTn7TTO8xG/p xUpw== X-Gm-Message-State: AA+aEWb3soq/0+/XGn3Gw85HbKcEgaLJ85sop3cNVdtiozd13ccPc84v KvnkOQDyNTHzVWv1GODGBLcA3BtL5qA= X-Google-Smtp-Source: AFSGD/XrfnY0Tj1dNADKk7tCOm0tn7gcjhN1ya9cJCoPe6iJyKDT7DfzFmPUg+tj4fOef1YlKGDviQ== X-Received: by 2002:a63:cc12:: with SMTP id x18mr24081161pgf.33.1543229003370; Mon, 26 Nov 2018 02:43:23 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([49.207.53.74]) by smtp.googlemail.com with ESMTPSA id x125-v6sm9627186pfx.38.2018.11.26.02.43.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Nov 2018 02:43:22 -0800 (PST) From: Anup Patel To: Rick Chen Date: Mon, 26 Nov 2018 16:09:06 +0530 Message-Id: <20181126103910.14457-1-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v5 0/4] RISC-V S-mode support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patchset allows us runing u-boot in S-mode which is useful on platforms where M-mode runtime firmware is an independent firmware and u-boot is used as last stage OS bootloader. The patchset based upon git://git.denx.de/u-boot-riscv.git and is tested on QEMU in both M-mode and S-mode. For S-mode testing, we have used u-boot.bin as payload of latest BBL (at commit 6ebd0f2a46255d0c76dad3c05b16c1d154795d26) applied with following changes: Changes since v4: - Rebased series based on commit 52923c6db7f00e0197ec894c8c1bb8a7681974bb of git://git.denx.de/u-boot-riscv.git - Added a patch to remove redundant a2 store on DRAM base. This store was creating problem booting U-Boot in S-mode using BBL. Changes since v3: - Replaced 'u-boot' with 'U-Boot' in commit message - Dropped 'an' in RISCV_SMODE kconfig option help message - Added appropriate #ifdef in arch/riscv/lib/interrupts.c Changes since v2: - Dropped 'default n" from RISCV_SMODE kconfig option - Replaced '-smode_' in defconfig names with '_smode_' Changes since v1: - Rebased upon latest git://git.denx.de/u-boot-riscv.git - Add details in cover letter for running u-boot in S-mode using BBL Anup Patel (4): riscv: Add kconfig option to run U-Boot in S-mode riscv: qemu: Use different SYS_TEXT_BASE for S-mode riscv: Add S-mode defconfigs for QEMU virt machine riscv: Remove redundant a2 store on DRAM base in start.S arch/riscv/Kconfig | 5 ++++ arch/riscv/cpu/start.S | 35 +++++++++++++++++++++++-- arch/riscv/include/asm/encoding.h | 2 ++ arch/riscv/lib/interrupts.c | 36 +++++++++++++++++++------- board/emulation/qemu-riscv/Kconfig | 3 ++- board/emulation/qemu-riscv/MAINTAINERS | 2 ++ configs/qemu-riscv32_smode_defconfig | 10 +++++++ configs/qemu-riscv64_smode_defconfig | 11 ++++++++ 8 files changed, 92 insertions(+), 12 deletions(-) create mode 100644 configs/qemu-riscv32_smode_defconfig create mode 100644 configs/qemu-riscv64_smode_defconfig diff --git a/machine/emulation.c b/machine/emulation.c index 132e977..def75e1 100644 --- a/machine/emulation.c +++ b/machine/emulation.c @@ -162,6 +162,12 @@ static inline int emulate_read_csr(int num, uintptr_t mstatus, uintptr_t* result switch (num) { + case CSR_MISA: + *result = read_csr(misa); + return 0; + case CSR_MHARTID: + *result = read_csr(mhartid); + return 0; case CSR_CYCLE: if (!((counteren >> (CSR_CYCLE - CSR_CYCLE)) & 1)) return -1;