From patchwork Thu Nov 22 04:45:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1001535 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="pYVgKFJM"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430n352J0bz9s5c for ; Thu, 22 Nov 2018 15:46:40 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id AB53EC21EE5; Thu, 22 Nov 2018 04:45:42 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 640E2C21EBD; Thu, 22 Nov 2018 04:45:32 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 45DEAC21EDC; Thu, 22 Nov 2018 04:45:29 +0000 (UTC) Received: from mail-pl1-f196.google.com (mail-pl1-f196.google.com [209.85.214.196]) by lists.denx.de (Postfix) with ESMTPS id 6D017C21EFC for ; Thu, 22 Nov 2018 04:45:25 +0000 (UTC) Received: by mail-pl1-f196.google.com with SMTP id 101so2299784pld.6 for ; Wed, 21 Nov 2018 20:45:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BlYqY81qinbcVzqhu+98cKnUTNlhPTCPVNcsraI/tcU=; b=pYVgKFJMHM+st5zbOy2HcJSwdCBIHijBTNXbOwzLbCfZ/vNZEtt5ELK5FzIcMTm9wx okVE3tblccxfGafn4M1RQFmvNWOYkrWXfz3QukMxGZj2kvUIq7reifiBxeDeOJTY2sma OmIBjclgKH5a8ml0ViZUmoiNr1DtNh7BbYXmSFZH7ibGmDXMWQduq+VZ3QoEMoRb4KAT /wnchK48KFLrZNR/kte/mFcxVB2/4yCK33y/dVUefN+MHPMJvBX/jiy/72wUovo86VMh 6nfso9G0wZAAdsjyX1IHwlpN9N1lDgn90Egjj0zMVjzFaKi0hPvb5qVHLz1/qZWHa9it 9Xzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BlYqY81qinbcVzqhu+98cKnUTNlhPTCPVNcsraI/tcU=; b=JGuiiMws3P6tgAy0fy+keAuwBof4EE5Hp4NFGPwibFBMDuC7/GSdb8e3NKFmSMIdk0 Giuffe5vH40tFfEdKXeO2r/G7OxRnRdVUHoLFPhC8R17t2PT54AvnUUzIFqUmiFQnJf/ fiiWT9tkdh6TZ9j3sR+hu2l8gYMLhM89C3GjuNphCsEPkL+7Ao+1p/F64XLKmknH/Vo8 vu9Gc3ls5FDC/LwK00aFnitOxezLJLEgKwYmHPQgsbmbNP+XEoLPlmV3RE02/ivN5l60 +UKp7UVEKcTXF3i/7UIgS56O6U10pWg+tWN7+nE47kroq+mgNnSsuvHa5uozTqGoecLx S02w== X-Gm-Message-State: AA+aEWZxffOsEOqTmoUM5wrZau1AdKc0Ayc4FCiRcqNYUwmLpOZb2Erj E6YlgMLb5puAKOQ2pU+7EhtXhA== X-Google-Smtp-Source: AFSGD/U9Gt6PBpqQIalnXXulZMYfGn1VqPp7qDvn2VMSt0VkMleIyxY5O6MmulflPsnvew91TUfrIQ== X-Received: by 2002:a63:5765:: with SMTP id h37mr8649488pgm.423.1542861923754; Wed, 21 Nov 2018 20:45:23 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([49.207.51.56]) by smtp.googlemail.com with ESMTPSA id o23-v6sm30869636pfa.112.2018.11.21.20.45.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 21 Nov 2018 20:45:23 -0800 (PST) From: Anup Patel To: Rick Chen Date: Thu, 22 Nov 2018 10:15:01 +0530 Message-Id: <20181122044503.18334-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181122044503.18334-1-anup@brainfault.org> References: <20181122044503.18334-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v4 1/3] riscv: Add kconfig option to run U-Boot in S-mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s CSRs instead of m CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/Kconfig | 5 +++++ arch/riscv/cpu/start.S | 33 ++++++++++++++++++++++++++++ arch/riscv/include/asm/encoding.h | 2 ++ arch/riscv/lib/interrupts.c | 36 +++++++++++++++++++++++-------- 4 files changed, 67 insertions(+), 9 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3e0af55e71..732a357a99 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -55,6 +55,11 @@ config RISCV_ISA_C config RISCV_ISA_A def_bool y +config RISCV_SMODE + bool "Run in S-Mode" + help + Enable this option to build U-Boot for RISC-V S-Mode + config 32BIT bool diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 5af189b338..e4276e8e19 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -39,10 +39,18 @@ _start: mv s1, a1 la t0, trap_entry +#ifdef CONFIG_RISCV_SMODE + csrw stvec, t0 +#else csrw mtvec, t0 +#endif /* mask all interrupts */ +#ifdef CONFIG_RISCV_SMODE + csrw sie, zero +#else csrw mie, zero +#endif /* Enable cache */ jal icache_enable @@ -164,7 +172,11 @@ fix_rela_dyn: */ la t0, trap_entry add t0, t0, t6 +#ifdef CONFIG_RISCV_SMODE + csrw stvec, t0 +#else csrw mtvec, t0 +#endif clear_bss: la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ @@ -236,17 +248,34 @@ trap_entry: SREG x29, 29*REGBYTES(sp) SREG x30, 30*REGBYTES(sp) SREG x31, 31*REGBYTES(sp) +#ifdef CONFIG_RISCV_SMODE + csrr a0, scause + csrr a1, sepc +#else csrr a0, mcause csrr a1, mepc +#endif mv a2, sp jal handle_trap +#ifdef CONFIG_RISCV_SMODE + csrw sepc, a0 +#else csrw mepc, a0 +#endif +#ifdef CONFIG_RISCV_SMODE +/* + * Remain in S-mode after sret + */ + li t0, SSTATUS_SPP + csrs sstatus, t0 +#else /* * Remain in M-mode after mret */ li t0, MSTATUS_MPP csrs mstatus, t0 +#endif LREG x1, 1*REGBYTES(sp) LREG x2, 2*REGBYTES(sp) LREG x3, 3*REGBYTES(sp) @@ -279,4 +308,8 @@ trap_entry: LREG x30, 30*REGBYTES(sp) LREG x31, 31*REGBYTES(sp) addi sp, sp, 32*REGBYTES +#ifdef CONFIG_RISCV_SMODE + sret +#else mret +#endif diff --git a/arch/riscv/include/asm/encoding.h b/arch/riscv/include/asm/encoding.h index 9ea50ce640..153f5af2ff 100644 --- a/arch/riscv/include/asm/encoding.h +++ b/arch/riscv/include/asm/encoding.h @@ -143,6 +143,8 @@ # define MCAUSE_CAUSE MCAUSE32_CAUSE #endif +#define SCAUSE_INT MCAUSE_INT + #define RISCV_PGSHIFT 12 #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index 903a1c4cd5..8793f233d0 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -34,17 +34,35 @@ int disable_interrupts(void) return 0; } -ulong handle_trap(ulong mcause, ulong epc, struct pt_regs *regs) +ulong handle_trap(ulong cause, ulong epc, struct pt_regs *regs) { - ulong is_int; + ulong is_irq, irq; - is_int = (mcause & MCAUSE_INT); - if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) - external_interrupt(0); /* handle_m_ext_interrupt */ - else if ((is_int) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)) - timer_interrupt(0); /* handle_m_timer_interrupt */ - else - _exit_trap(mcause, epc, regs); +#ifdef CONFIG_RISCV_SMODE + is_irq = (cause & SCAUSE_INT); + irq = (cause & ~SCAUSE_INT); +#else + is_irq = (cause & MCAUSE_INT); + irq = (cause & ~MCAUSE_INT); +#endif + + if (is_irq) { + switch (irq) { + case IRQ_M_EXT: + case IRQ_S_EXT: + external_interrupt(0); /* handle external interrupt */ + break; + case IRQ_M_TIMER: + case IRQ_S_TIMER: + timer_interrupt(0); /* handle timer interrupt */ + break; + default: + _exit_trap(cause, epc, regs); + break; + }; + } else { + _exit_trap(cause, epc, regs); + } return epc; }