From patchwork Thu Nov 22 04:45:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1001534 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="QoVG3+mr"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 430n1q01bFz9s5c for ; Thu, 22 Nov 2018 15:45:31 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2AD36C21EA1; Thu, 22 Nov 2018 04:45:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A7E03C21EA1; Thu, 22 Nov 2018 04:45:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 42BD6C21EA1; Thu, 22 Nov 2018 04:45:21 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id 9C5B7C21E47 for ; Thu, 22 Nov 2018 04:45:20 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id a14so8574275plm.12 for ; Wed, 21 Nov 2018 20:45:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=laVnq6B3/90vCTZjZuyoA/nZ8a2ksXM1OSAdL+gZvio=; b=QoVG3+mrUQmZvoJKPqwClD9YKqg8ecd7Dk5gN6+Ai4wrNqiDMhRXNATQx9mv9cf72O VQcNcOGX3uJVHq2d4epkcBkRlLYJzGj8TK+WnDPC6DYaeI5ip9bPMUaE8uBN2ArAbqQU DOXulgYfcO/9mq5OE6wrDbag/kvMnZcEQ+KCZBuqKg5XIZZh14pY0Psfupqo5NyBMaJ8 IoqigQlEzHyXmQZNg/fsTZePvMslOli/IbcvZapiodmWRg0+nC8xfbDfvpDnAhsPMgmf 7Wx0e2N2qXy7TihDtql229bXb7lespBBJcUpGqDdxrAv/CwV8DClJ+tRRwlu5MPAGLOR OjIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=laVnq6B3/90vCTZjZuyoA/nZ8a2ksXM1OSAdL+gZvio=; b=uUHZUQq+l9y2xnFGNL5gcQXzW+64bOfMzC9OArfNw4ctMrDGVym5Y7+zJpO8qlGAHi VBpP7LlpviLuPZFr5B9lplIWsqc/io3dr/3WM4MP4fLk19HYmvF0BNp4dnjmikYx5T0a rjtwGD/tVB4CtCk+nM7QVVhkx1PKYnDazSEqeWzsf5RCMbUCy3ua5FENtHgU/pr6mce3 iEDWQtW90MLE77U7/evKKEmN2DOuEgKRuto2ckmWDxlomwyz1vJig/gR3klPWsIqFNDe dqoEhviebTAVkQG+cBZltJ1xJs2azuuhuUQdtsMzs4gQdO65s33b/I7AJpJLSWJwB8ZW RSAw== X-Gm-Message-State: AA+aEWZIXrsluk5HgpDnoqNrfMNLOgAILs1KM6KMRNiPtTvWzi1lUpS/ DbbP7OdQUgBAhgVhcQUgj55CnA== X-Google-Smtp-Source: AFSGD/WhNJrzgo3unkLKfdzpQgZYNlYMSaxGt3mriB1WzQbbTRlt5n4Y0FthsmheONby3AUVmmGn/A== X-Received: by 2002:a17:902:b60a:: with SMTP id b10mr9181745pls.303.1542861918880; Wed, 21 Nov 2018 20:45:18 -0800 (PST) Received: from anup-ubuntu64.qualcomm.com ([49.207.51.56]) by smtp.googlemail.com with ESMTPSA id o23-v6sm30869636pfa.112.2018.11.21.20.45.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 21 Nov 2018 20:45:18 -0800 (PST) From: Anup Patel To: Rick Chen Date: Thu, 22 Nov 2018 10:15:00 +0530 Message-Id: <20181122044503.18334-1-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v4 0/3] RISC-V S-mode support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patchset allows us runing u-boot in S-mode which is useful on platforms where M-mode runtime firmware is an independent firmware and u-boot is used as last stage OS bootloader. The patchset based upon git://git.denx.de/u-boot-riscv.git and is tested on QEMU in both M-mode and S-mode. For S-mode testing, we have used u-boot.bin as payload of latest BBL (at commit 6ebd0f2a46255d0c76dad3c05b16c1d154795d26) applied with following changes: Changes since v3: - Replaced 'u-boot' with 'U-Boot' in commit message - Dropped 'an' in RISCV_SMODE kconfig option help message - Added appropriate #ifdef in arch/riscv/lib/interrupts.c Changes since v2: - Dropped 'default n" from RISCV_SMODE kconfig option - Replaced '-smode_' in defconfig names with '_smode_' Changes since v1: - Rebased upon latest git://git.denx.de/u-boot-riscv.git - Add details in cover letter for running u-boot in S-mode using BBL Anup Patel (3): riscv: Add kconfig option to run U-Boot in S-mode riscv: qemu: Use different SYS_TEXT_BASE for S-mode riscv: Add S-mode defconfigs for QEMU virt machine arch/riscv/Kconfig | 5 ++++ arch/riscv/cpu/start.S | 33 +++++++++++++++++++++++ arch/riscv/include/asm/encoding.h | 2 ++ arch/riscv/lib/interrupts.c | 36 +++++++++++++++++++------- board/emulation/qemu-riscv/Kconfig | 3 ++- board/emulation/qemu-riscv/MAINTAINERS | 2 ++ configs/qemu-riscv32_smode_defconfig | 10 +++++++ configs/qemu-riscv64_smode_defconfig | 11 ++++++++ 8 files changed, 92 insertions(+), 10 deletions(-) create mode 100644 configs/qemu-riscv32_smode_defconfig create mode 100644 configs/qemu-riscv64_smode_defconfig diff --git a/machine/emulation.c b/machine/emulation.c index 132e977..def75e1 100644 --- a/machine/emulation.c +++ b/machine/emulation.c @@ -162,6 +162,12 @@ static inline int emulate_read_csr(int num, uintptr_t mstatus, uintptr_t* result switch (num) { + case CSR_MISA: + *result = read_csr(misa); + return 0; + case CSR_MHARTID: + *result = read_csr(mhartid); + return 0; case CSR_CYCLE: if (!((counteren >> (CSR_CYCLE - CSR_CYCLE)) & 1)) return -1;