From patchwork Wed Nov 21 03:41:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1000904 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="VTQDLTXW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4307h03n6Vz9s0n for ; Wed, 21 Nov 2018 14:42:56 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1E65CC221F4; Wed, 21 Nov 2018 03:42:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_SORBS_WEB, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 815AEC221FD; Wed, 21 Nov 2018 03:42:00 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D075CC221F6; Wed, 21 Nov 2018 03:41:45 +0000 (UTC) Received: from mail-pl1-f195.google.com (mail-pl1-f195.google.com [209.85.214.195]) by lists.denx.de (Postfix) with ESMTPS id EDBEBC221BB for ; Wed, 21 Nov 2018 03:41:41 +0000 (UTC) Received: by mail-pl1-f195.google.com with SMTP id t13so3372696ply.13 for ; Tue, 20 Nov 2018 19:41:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sgZKrUzTMwrvuntlfAFzFhjtf8tlpgwjy4a4g9ZDlpo=; b=VTQDLTXWnEYlorKhG6lb2xIuhblNA0bdXS6ujKHvYLkYBsj8jbNJNCH0iWiPs4eudK /9u2j0OC12F+Q8qQwjasgaOrBX5OfUtdBq8py5BKpAm0Ak1RCInMeYXe/63jtttswuOo lP5GbBltvekzRBNLk89H9uvW49KwA+pwbxayDMJxU8OA83r15WSgVgKWSQwrKzCNdaik tny87b/QnsW+hiXqRJT9X3rtpmXdYZz6qsuNGyPEyCxGM1Gut7/PTlpueWonnBKZ8kED +NACQStUKMxPWoJuywGqTmaBBfN5IqSecxMPpOL6ZBqquaj3lyxJR5VV+cBm42oMjMXM 0ewQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sgZKrUzTMwrvuntlfAFzFhjtf8tlpgwjy4a4g9ZDlpo=; b=FxZJVZk77D56dg3szlEo2tpw21cp9hsTiCJlM2NnqlzuaJxuQD0j44P8YGyXYzH4m/ jBXZNu6oe4zCfqYgqSaCjtB20NdiEIlITaPx9d9R/6uS8sQcAoL0HexyJkmi2GWP0SFc v7v0GvYpIu3mW/Tf0fI3tZA8BVoasT5YOEvDYAVtwcPjQpnTjLqWzOECgAHiPVUTQVy9 mvGDtQ+zg6ZgeBauo5O5achIYx0kT3/plF/RhNj7FrgQST576CicybKhEQ6QDUOWrnAh h13eaHAX+TGclUXs1DiKHWj+iofyyhG3nE4c6wQ4EJyVwUBqaxM8TdxcBBmtEXL16SEb 4NAw== X-Gm-Message-State: AA+aEWZpVLjKkIbHCYRbOfsovH0TaNfgO5RYImpQzKst+nY94VUIk+kL 0BACQKm/EecpeosV/pLsD208mQ== X-Google-Smtp-Source: AFSGD/V5HNtxyQYA+++VMiFKduYjHH9kr7YjE7zGilFGEYHmIVYsDyiYbCpRaHzaWZFDzvFYt07UwQ== X-Received: by 2002:a17:902:f44:: with SMTP id 62mr2775917ply.38.1542771700318; Tue, 20 Nov 2018 19:41:40 -0800 (PST) Received: from localhost.localdomain ([106.51.20.239]) by smtp.googlemail.com with ESMTPSA id b185sm53870623pga.85.2018.11.20.19.41.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 19:41:39 -0800 (PST) From: Anup Patel To: Rick Chen Date: Wed, 21 Nov 2018 09:11:12 +0530 Message-Id: <20181121034112.7136-4-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181121034112.7136-1-anup@brainfault.org> References: <20181121034112.7136-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v3 3/3] riscv: Add S-mode defconfigs for QEMU virt machine X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds S-mode defconfigs for QEMU virt machine so that we can run u-boot in S-mode on QEMU using M-mode runtime firmware (BBL or equivalent). Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Lukas Auer --- board/emulation/qemu-riscv/MAINTAINERS | 2 ++ configs/qemu-riscv32_smode_defconfig | 10 ++++++++++ configs/qemu-riscv64_smode_defconfig | 11 +++++++++++ 3 files changed, 23 insertions(+) create mode 100644 configs/qemu-riscv32_smode_defconfig create mode 100644 configs/qemu-riscv64_smode_defconfig diff --git a/board/emulation/qemu-riscv/MAINTAINERS b/board/emulation/qemu-riscv/MAINTAINERS index 3c6eb4f844..c701c83d77 100644 --- a/board/emulation/qemu-riscv/MAINTAINERS +++ b/board/emulation/qemu-riscv/MAINTAINERS @@ -4,4 +4,6 @@ S: Maintained F: board/emulation/qemu-riscv/ F: include/configs/qemu-riscv.h F: configs/qemu-riscv32_defconfig +F: configs/qemu-riscv32_smode_defconfig F: configs/qemu-riscv64_defconfig +F: configs/qemu-riscv64_smode_defconfig diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig new file mode 100644 index 0000000000..0a84ec1874 --- /dev/null +++ b/configs/qemu-riscv32_smode_defconfig @@ -0,0 +1,10 @@ +CONFIG_RISCV=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig new file mode 100644 index 0000000000..b012443370 --- /dev/null +++ b/configs/qemu-riscv64_smode_defconfig @@ -0,0 +1,11 @@ +CONFIG_RISCV=y +CONFIG_TARGET_QEMU_VIRT=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_FIT=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +# CONFIG_CMD_MII is not set +CONFIG_OF_PRIOR_STAGE=y