From patchwork Wed Nov 21 03:41:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1000903 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="ewIot6aB"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4307g70C8Gz9s0n for ; Wed, 21 Nov 2018 14:42:10 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B8F87C221F2; Wed, 21 Nov 2018 03:41:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_SORBS_WEB, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 55B18C221C9; Wed, 21 Nov 2018 03:41:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2C837C221DE; Wed, 21 Nov 2018 03:41:35 +0000 (UTC) Received: from mail-pl1-f194.google.com (mail-pl1-f194.google.com [209.85.214.194]) by lists.denx.de (Postfix) with ESMTPS id 4FD5EC221D3 for ; Wed, 21 Nov 2018 03:41:32 +0000 (UTC) Received: by mail-pl1-f194.google.com with SMTP id a14so3376281plm.12 for ; Tue, 20 Nov 2018 19:41:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=uBReNbm1kJaUd+OF231qi92goY6xRjNQkXb114CHmps=; b=ewIot6aB6m1H0ynZ+vT4w8G5xcAoZ9gLh2cYXHb8EhBgB5lkQ1uOKG2RuuVDDnhDuL 0kfxVVFAUqn8fPZDcFNq4gi0kICQ97xpgLRO5utTyUCYj+VE7/axIQQaTHn8Eck8iGf/ d6wMOCEPKbMt1KDzbKsikmcIZgD4GBeKDOeojtgM5NUGLkY8sg5HnOVQGjM4JOJrtjS4 RYG+vIwWzQYNcSBAj3rDHDpYSJMPK5dVRLjX6Ymc/fXAqaIsoF6o2oIr0KvsHht+0KBG 5EsMVQZjD01IlHPhCblTvadsKCF0bgMbLnodsNV6hzljsWT14OeU7lnLgALfy836Y1pF X+Sg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=uBReNbm1kJaUd+OF231qi92goY6xRjNQkXb114CHmps=; b=SfnftfUsR/Ug9an42LdauDaobqb5eDIlND2hArgWRSe1ReWtOIPCOwfvQ1hvbH5AgB 8DXKxKviXjHJ1orzYrON/ImVbrzHpWe8w0gerd4zRjK0uiLefrHUEalic1R3leVuL/xq Bey9aWcw5OMmnwTPvgiPXlLAmWP3AnRjFMzbC3DHeZBYWyHhdLvGJeLuD7Je497zyTgL Jtl/ymca76HhBUNvrZlXrdkE8Ukj1YkQMIvjEXm0iU8V7V6LN99DFwFha2+vi27Ap45P Fjfo0gx5OmdKnmCGHuKlc9dWDAWCpTls7NLPyuWc/9euG/ZD4p4T1UazbA3c/Gs/g7lQ SbJA== X-Gm-Message-State: AGRZ1gIYWuATEp91C1oiukbm+vjL4vL38d66fAGjVkdL46ffAfCWoqZB 4WN9ukWqLPO+nJ5gFRDt/8u0Lg== X-Google-Smtp-Source: AJdET5cN9DPzbp0FulHWUzB+CZ7Pmoq3KXutPuXAb1Y0xWsaaAGAbgcfQ9I2ZPC12SqX8ocan2i7ug== X-Received: by 2002:a62:5ac3:: with SMTP id o186-v6mr5237877pfb.40.1542771690715; Tue, 20 Nov 2018 19:41:30 -0800 (PST) Received: from localhost.localdomain ([106.51.20.239]) by smtp.googlemail.com with ESMTPSA id b185sm53870623pga.85.2018.11.20.19.41.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 19:41:30 -0800 (PST) From: Anup Patel To: Rick Chen Date: Wed, 21 Nov 2018 09:11:10 +0530 Message-Id: <20181121034112.7136-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181121034112.7136-1-anup@brainfault.org> References: <20181121034112.7136-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v3 1/3] riscv: Add kconfig option to run u-boot in S-mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds kconfig option RISCV_SMODE to run u-boot in S-mode. When this opition is enabled we use s CSRs instead of m CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Lukas Auer --- arch/riscv/Kconfig | 5 +++++ arch/riscv/cpu/start.S | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3e0af55e71..8f2139ff60 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -55,6 +55,11 @@ config RISCV_ISA_C config RISCV_ISA_A def_bool y +config RISCV_SMODE + bool "Run in S-Mode" + help + Enable this option to build an U-Boot for RISC-V S-Mode + config 32BIT bool diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 5af189b338..e4276e8e19 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -39,10 +39,18 @@ _start: mv s1, a1 la t0, trap_entry +#ifdef CONFIG_RISCV_SMODE + csrw stvec, t0 +#else csrw mtvec, t0 +#endif /* mask all interrupts */ +#ifdef CONFIG_RISCV_SMODE + csrw sie, zero +#else csrw mie, zero +#endif /* Enable cache */ jal icache_enable @@ -164,7 +172,11 @@ fix_rela_dyn: */ la t0, trap_entry add t0, t0, t6 +#ifdef CONFIG_RISCV_SMODE + csrw stvec, t0 +#else csrw mtvec, t0 +#endif clear_bss: la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ @@ -236,17 +248,34 @@ trap_entry: SREG x29, 29*REGBYTES(sp) SREG x30, 30*REGBYTES(sp) SREG x31, 31*REGBYTES(sp) +#ifdef CONFIG_RISCV_SMODE + csrr a0, scause + csrr a1, sepc +#else csrr a0, mcause csrr a1, mepc +#endif mv a2, sp jal handle_trap +#ifdef CONFIG_RISCV_SMODE + csrw sepc, a0 +#else csrw mepc, a0 +#endif +#ifdef CONFIG_RISCV_SMODE +/* + * Remain in S-mode after sret + */ + li t0, SSTATUS_SPP + csrs sstatus, t0 +#else /* * Remain in M-mode after mret */ li t0, MSTATUS_MPP csrs mstatus, t0 +#endif LREG x1, 1*REGBYTES(sp) LREG x2, 2*REGBYTES(sp) LREG x3, 3*REGBYTES(sp) @@ -279,4 +308,8 @@ trap_entry: LREG x30, 30*REGBYTES(sp) LREG x31, 31*REGBYTES(sp) addi sp, sp, 32*REGBYTES +#ifdef CONFIG_RISCV_SMODE + sret +#else mret +#endif