From patchwork Tue Nov 20 11:29:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1000411 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="A0iYp+db"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42zk5r03nWz9s3l for ; Tue, 20 Nov 2018 22:30:23 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 95DC7C22022; Tue, 20 Nov 2018 11:30:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 76D67C22044; Tue, 20 Nov 2018 11:30:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 816E7C22043; Tue, 20 Nov 2018 11:29:55 +0000 (UTC) Received: from mail-pg1-f196.google.com (mail-pg1-f196.google.com [209.85.215.196]) by lists.denx.de (Postfix) with ESMTPS id 9BADAC22006 for ; Tue, 20 Nov 2018 11:29:51 +0000 (UTC) Received: by mail-pg1-f196.google.com with SMTP id d72so774363pga.9 for ; Tue, 20 Nov 2018 03:29:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=LlCwKDErZLaNmwGn+7rfoVTjpeAgbsjwgt4dvvD61GQ=; b=A0iYp+dbf3vQrsGGyLsxSqHzGIRNRpbo0jZCldHKIZd0QOyAgdjX3O9gtwmhWELD4o OMgdalONLTo0nt5UB6x+jYD74MHh3SdbLnPhh1eSZkzoD8ZgSenh/q/Bvqukp7zU33pH vytqP1C6+jE/qFr3KYJzVHRy09TmjJNCZ3eM9ft+qN21LXEtn04kLxH6O2+0EMTc7gqw mj3UWBy9ngTkKajppZeVElhk2iVUhP9KXZfVf/wET9WpwSyeRm7sSazLfXz8+cWtDSGf R3Af22K0x86HvniJCgVX1rEraFyNvrsumYPf9ufEigeR4gef8IkahGm3Z1qInEJIcLw5 0eMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=LlCwKDErZLaNmwGn+7rfoVTjpeAgbsjwgt4dvvD61GQ=; b=LOw41aAM1oEm+wfpyg/ixSxdkxNhqOaJbxyrxjo8vGSyyRHSOscl2eM333ziGdLubn +J33yVwneaNsxX+UtWqtv7dyWtTzvfpfF7FFQst5vj/CrR6/oftRMszG5o9Dfc+uQrRm sKpzNgM6KjCrrP1ZhgIQwkY5kgSAr51507YLxv9iN3ao78AEWLov6oECC1aUiKr1cB2f tMJ5vcQjHQH/S10pOf6OcVP3T/P0SRZYb+Ktk4Fy0wIzA9RpDXnh6ZDyrsSKs+kK0S+A 4VAGx4c8dRg90mQ+nMG075heR6MCzMgnmZw1IoOZi03tgXJd2oOiRxiq5YhbMSpNISHn RzqA== X-Gm-Message-State: AGRZ1gK84ZlEXYSlR8kmAUpo/U1i3nCw7SB62h2LYzT9oKVb+dI2bPX5 ZtV2d4GpDKjY7H7JBQAet4M+Ig== X-Google-Smtp-Source: AFSGD/VE2RP7i/CKT283r8VZvLYXggllcqkwxTAVDZXCB/Dm6yVmDQDEGGxRRILBOBMKr99+P1prcA== X-Received: by 2002:a63:801:: with SMTP id 1mr1502318pgi.275.1542713389958; Tue, 20 Nov 2018 03:29:49 -0800 (PST) Received: from localhost.localdomain ([106.51.16.59]) by smtp.googlemail.com with ESMTPSA id m10-v6sm97725026pfg.180.2018.11.20.03.29.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 03:29:49 -0800 (PST) From: Anup Patel To: Rick Chen Date: Tue, 20 Nov 2018 16:59:31 +0530 Message-Id: <20181120112933.23700-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181120112933.23700-1-anup@brainfault.org> References: <20181120112933.23700-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v2 1/3] riscv: Add kconfig option to run u-boot in S-mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds kconfig option RISCV_SMODE to run u-boot in S-mode. When this opition is enabled we use s CSRs instead of m CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. Eventually, we will have patches to avoid accessing misa and mhartid from S-mode. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng --- arch/riscv/Kconfig | 6 ++++++ arch/riscv/cpu/start.S | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 3e0af55e71..88bc0d2a43 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -55,6 +55,12 @@ config RISCV_ISA_C config RISCV_ISA_A def_bool y +config RISCV_SMODE + bool "Run in S-Mode" + default n + help + Enable this option to build an U-Boot for RISC-V S-Mode + config 32BIT bool diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 5af189b338..e4276e8e19 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -39,10 +39,18 @@ _start: mv s1, a1 la t0, trap_entry +#ifdef CONFIG_RISCV_SMODE + csrw stvec, t0 +#else csrw mtvec, t0 +#endif /* mask all interrupts */ +#ifdef CONFIG_RISCV_SMODE + csrw sie, zero +#else csrw mie, zero +#endif /* Enable cache */ jal icache_enable @@ -164,7 +172,11 @@ fix_rela_dyn: */ la t0, trap_entry add t0, t0, t6 +#ifdef CONFIG_RISCV_SMODE + csrw stvec, t0 +#else csrw mtvec, t0 +#endif clear_bss: la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ @@ -236,17 +248,34 @@ trap_entry: SREG x29, 29*REGBYTES(sp) SREG x30, 30*REGBYTES(sp) SREG x31, 31*REGBYTES(sp) +#ifdef CONFIG_RISCV_SMODE + csrr a0, scause + csrr a1, sepc +#else csrr a0, mcause csrr a1, mepc +#endif mv a2, sp jal handle_trap +#ifdef CONFIG_RISCV_SMODE + csrw sepc, a0 +#else csrw mepc, a0 +#endif +#ifdef CONFIG_RISCV_SMODE +/* + * Remain in S-mode after sret + */ + li t0, SSTATUS_SPP + csrs sstatus, t0 +#else /* * Remain in M-mode after mret */ li t0, MSTATUS_MPP csrs mstatus, t0 +#endif LREG x1, 1*REGBYTES(sp) LREG x2, 2*REGBYTES(sp) LREG x3, 3*REGBYTES(sp) @@ -279,4 +308,8 @@ trap_entry: LREG x30, 30*REGBYTES(sp) LREG x31, 31*REGBYTES(sp) addi sp, sp, 32*REGBYTES +#ifdef CONFIG_RISCV_SMODE + sret +#else mret +#endif