From patchwork Tue Nov 20 09:14:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1000316 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="XQ9ZVCRq"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42zg6Q1H8Qz9s1x for ; Tue, 20 Nov 2018 20:15:42 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C0DA7C21FE4; Tue, 20 Nov 2018 09:14:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6FC19C2200F; Tue, 20 Nov 2018 09:14:48 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 074BCC21FD5; Tue, 20 Nov 2018 09:14:41 +0000 (UTC) Received: from mail-pf1-f193.google.com (mail-pf1-f193.google.com [209.85.210.193]) by lists.denx.de (Postfix) with ESMTPS id C1D09C21FF6 for ; Tue, 20 Nov 2018 09:14:37 +0000 (UTC) Received: by mail-pf1-f193.google.com with SMTP id q1so701556pfi.5 for ; Tue, 20 Nov 2018 01:14:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GYa/EeJp7AfZEkOwnSGlm0wYL50h08Nt+8cukouJA2Y=; b=XQ9ZVCRqhwG2IBuKIADja4Cn3+78YPadcMpcBzK2xzGjuLLUL8h64ovyrE0K8YqMab ozGycZonzoAsyFwlLhE1j9dcwuED28lw5ygvtGlhxDMFssE+F1fXjRA0HLzPCT4PKajF 7+LoIdgrfpoDTV9pzuEMcGGPW8RENZZ8x0Yp+AtCYjtmoYfvyc3QWYeDMeMji0N2d1u2 5p2ORBdBO0HcMoVXtbHRTJOo9Lpszkf80a7Kj1i8SU/5jhkRYEa/LqqeAzW+pTynP4Uo Y5Dbmsj0s+fP/vEaIRhRNtZSdFGkg5/bd2ToFiYr3T2ZrPwr6GrXDXCCpDbUDwX6aOk9 epsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GYa/EeJp7AfZEkOwnSGlm0wYL50h08Nt+8cukouJA2Y=; b=CX1qH1U/pkQeL6x9HHJv0gdbeU1WZN44DQUBQV1NTOGsuO4vtTJ1JLW3cX7uEMKzTo AoO+uHv/zrs5K8ddZg7O08O2QOR8IOC9vyV8Jn7TQkaRsutl1R7YpCFz6KY/YHeXkzAj 3aSyX8gctq3th8clETSOsEBg/CxwEyjBRgc4JxGJ4EWa+L45F9dPB9H7C80T0NrYauuq NmFSck8BShmW8ySPNl7YNZuifqfaYUvwT/uDnr/4G89C9H6SRZ4lmbIYTHcKViYt/Yg/ Duljh9AOZW0f+wq9+7MKwTGbu02zLr1Wb07fsqgIgVTpdYcFzAsMTUZWhQXF6R4vrhkJ UpRw== X-Gm-Message-State: AA+aEWZB3bLlDEdR86vi5I77bD/e3YEGrPYVlOA5RpEOuVw7iXYT1td0 Gjxo8kirtjsbyCftUiUcKiLJJg== X-Google-Smtp-Source: AFSGD/ULLYwz6znub4zey+6HL7VWaaigJL1C1K/K4HXfN5oOXfGNFUzXNR/v+nK76OTU4pP6RmF7QQ== X-Received: by 2002:a63:484c:: with SMTP id x12mr1149408pgk.375.1542705276002; Tue, 20 Nov 2018 01:14:36 -0800 (PST) Received: from localhost.localdomain ([106.51.16.59]) by smtp.googlemail.com with ESMTPSA id d80sm92810987pfm.146.2018.11.20.01.14.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 01:14:35 -0800 (PST) From: Anup Patel To: Rick Chen Date: Tue, 20 Nov 2018 14:44:17 +0530 Message-Id: <20181120091419.6575-2-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181120091419.6575-1-anup@brainfault.org> References: <20181120091419.6575-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH 1/3] riscv: Add kconfig option to run u-boot in S-mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds kconfig option RISCV_SMODE to run u-boot in S-mode. When this opition is enabled we use s CSRs instead of m CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. Eventually, we will have patches to avoid accessing misa and mhartid from S-mode. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 6 ++++++ arch/riscv/cpu/start.S | 31 +++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 168ca3de7c..0ee3bcc3c5 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -37,6 +37,12 @@ config CPU_RISCV_64 endchoice +config RISCV_SMODE + bool "Run in S-Mode" + default n + help + Enable this option to build an U-Boot for RISC-V S-Mode + config 32BIT bool diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 7cd7755190..669d3bde92 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -47,9 +47,15 @@ handle_reset: li t0, CONFIG_SYS_SDRAM_BASE SREG a2, 0(t0) la t0, trap_entry +#ifdef CONFIG_RISCV_SMODE + csrw stvec, t0 + csrwi sstatus, 0 + csrwi sie, 0 +#else csrw mtvec, t0 csrwi mstatus, 0 csrwi mie, 0 +#endif /* * Do CPU critical regs init only at reboot, @@ -171,7 +177,11 @@ fix_rela_dyn: */ la t0, trap_entry add t0, t0, t6 +#ifdef CONFIG_RISCV_SMODE + csrw stvec, t0 +#else csrw mtvec, t0 +#endif clear_bss: la t0, __bss_start /* t0 <- rel __bss_start in FLASH */ @@ -241,17 +251,34 @@ trap_entry: SREG x29, 29*REGBYTES(sp) SREG x30, 30*REGBYTES(sp) SREG x31, 31*REGBYTES(sp) +#ifdef CONFIG_RISCV_SMODE + csrr a0, scause + csrr a1, sepc +#else csrr a0, mcause csrr a1, mepc +#endif mv a2, sp jal handle_trap +#ifdef CONFIG_RISCV_SMODE + csrw sepc, a0 +#else csrw mepc, a0 +#endif +#ifdef CONFIG_RISCV_SMODE +/* + * Remain in S-mode after sret + */ + li t0, SSTATUS_SPP + csrs sstatus, t0 +#else /* * Remain in M-mode after mret */ li t0, MSTATUS_MPP csrs mstatus, t0 +#endif LREG x1, 1*REGBYTES(sp) LREG x2, 2*REGBYTES(sp) LREG x3, 3*REGBYTES(sp) @@ -284,7 +311,11 @@ trap_entry: LREG x30, 30*REGBYTES(sp) LREG x31, 31*REGBYTES(sp) addi sp, sp, 32*REGBYTES +#ifdef CONFIG_RISCV_SMODE + sret +#else mret +#endif #ifdef CONFIG_INIT_CRITICAL cpu_init_crit: