From patchwork Fri Nov 9 12:59:09 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukas Auer X-Patchwork-Id: 995520 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aisec.fraunhofer.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42s0x959cdz9sBZ for ; Sat, 10 Nov 2018 00:14:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 69437C220C8; Fri, 9 Nov 2018 13:07:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 85473C225C0; Fri, 9 Nov 2018 13:00:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E4EF1C225B5; Fri, 9 Nov 2018 13:00:15 +0000 (UTC) Received: from mail-edgeS23.fraunhofer.de (mail-edges23.fraunhofer.de [153.97.7.23]) by lists.denx.de (Postfix) with ESMTPS id 5F3DCC2258E for ; Fri, 9 Nov 2018 13:00:12 +0000 (UTC) X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A2EVAAAmhOVb/xoHYZlkGgEBAQEBAgEBAQEHAgEBAQGBVAIBAQEBCwGCA4FWOYxvli2JN4ZxDYRsAoMiIjcKDQEDAQECAQECAgJpHAyFPAZ5EFEhNgYOBYMhgWoDFAGpBYd6DYIZCQGHSIQqgVg/gRABhWiCdYUOAp8eLgcCgRGBBwSLUoMgCxiJT4cfLI15iUyBWSOBVTMaJIM7gicXg0OKWj4BMgGNQwEB X-IPAS-Result: A2EVAAAmhOVb/xoHYZlkGgEBAQEBAgEBAQEHAgEBAQGBVAIBAQEBCwGCA4FWOYxvli2JN4ZxDYRsAoMiIjcKDQEDAQECAQECAgJpHAyFPAZ5EFEhNgYOBYMhgWoDFAGpBYd6DYIZCQGHSIQqgVg/gRABhWiCdYUOAp8eLgcCgRGBBwSLUoMgCxiJT4cfLI15iUyBWSOBVTMaJIM7gicXg0OKWj4BMgGNQwEB X-IronPort-AV: E=Sophos;i="5.54,483,1534802400"; d="scan'208";a="7622514" Received: from mail-mtas26.fraunhofer.de ([153.97.7.26]) by mail-edgeS23.fraunhofer.de with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Nov 2018 14:00:12 +0100 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: A0ATAADxg+Vb/xBhWMBkGgEBAQEBAgEBAQEHAgEBAQGBVAIBAQEBCwGDOCE5jG+WLYk3hnENhGwCg0M3Cg0BAwEBAgEBAm0cDIU7BnkQUSE2Bg4FgyGBagMVqQSHeg2CGQkBh0iGAj+BEAGFaIJ1hQ4Cnx4uBwKBEYEHBItSgyALGIlPhx8sjXmJTIFZIoFVMxokgzuCJxeDQ4paPgMwAY1DAQE X-IronPort-AV: E=Sophos;i="5.54,483,1534802400"; d="scan'208";a="51714139" Received: from fgdemucivp01ltm.xch.fraunhofer.de (HELO FGDEMUCIMP12EXC.ads.fraunhofer.de) ([192.88.97.16]) by mail-mtaS26.fraunhofer.de with ESMTP/TLS/AES256-SHA; 09 Nov 2018 14:00:11 +0100 Received: from muc-nb-035.aisec.fraunhofer.de (10.80.233.51) by FGDEMUCIMP12EXC.ads.fraunhofer.de (10.80.232.43) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 9 Nov 2018 14:00:11 +0100 From: Lukas Auer To: Date: Fri, 9 Nov 2018 13:59:09 +0100 Message-ID: <20181109125923.7034-15-lukas.auer@aisec.fraunhofer.de> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20181109125923.7034-1-lukas.auer@aisec.fraunhofer.de> References: <20181109125923.7034-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.200.1013-24212.007 X-TM-AS-Result: No-0.872800-8.000000-31 X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No Cc: Greentime Hu Subject: [U-Boot] [PATCH v3 14/28] riscv: implement the invalidate_icache_* functions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Implement the functions invalidate_icache_range() and invalidate_icache_all(). RISC-V does not have instructions for explicit cache-control. The functions in this patch are implemented with the memory ordering instruction for synchronizing the instruction and data streams. This may be implemented as a cache flush or invalidate on simple processors, others may only invalidate the relevant cache lines. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- Changes in v3: None Changes in v2: None arch/riscv/lib/cache.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 1d67c49c2c..d642a38a07 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -12,6 +12,16 @@ void flush_dcache_range(unsigned long start, unsigned long end) void invalidate_icache_range(unsigned long start, unsigned long end) { + /* + * RISC-V does not have an instruction for invalidating parts of the + * instruction cache. Invalidate all of it instead. + */ + invalidate_icache_all(); +} + +void invalidate_icache_all(void) +{ + asm volatile ("fence.i" ::: "memory"); } void invalidate_dcache_range(unsigned long start, unsigned long end)