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[U-Boot,v2,08/29] riscv: enable -fdata-sections

Message ID	20181030125553.5230-9-lukas.auer@aisec.fraunhofer.de
State	Superseded
Delegated to:	Andes
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Lukas Auer <lukas.auer@aisec.fraunhofer.de> To: <u-boot@lists.denx.de> Date: Tue, 30 Oct 2018 13:55:31 +0100 Message-ID: <20181030125553.5230-9-lukas.auer@aisec.fraunhofer.de> In-Reply-To: <20181030125553.5230-1-lukas.auer@aisec.fraunhofer.de> References: <20181030125553.5230-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 Subject: [U-Boot] [PATCH v2 08/29] riscv: enable -fdata-sections Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	General fixes / cleanup for RISC-V and improvements to qemu-riscv \| expand [U-Boot,v2,00/29] General fixes / cleanup for RISC-V and improvements to qemu-riscv [U-Boot,v2,01/29] tools: .gitignore: add prelink-riscv [U-Boot,v2,02/29] dts: riscv: update makefile to also clean the RISC-V dts directory [U-Boot,v2,03/29] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I [U-Boot,v2,04/29] riscv: select CONFIG_PHYS_64BIT on RV64I systems [U-Boot,v2,05/29] riscv: add Kconfig entries for the C and A ISA extensions [U-Boot,v2,06/29] riscv: set -march and -mabi based on the Kconfig configuration [U-Boot,v2,07/29] riscv: add Kconfig entries for the code model [U-Boot,v2,08/29] riscv: enable -fdata-sections [U-Boot,v2,09/29] riscv: fix use of incorrectly sized variables [U-Boot,v2,10/29] riscv: make use of the barrier functions from Linux [U-Boot,v2,11/29] riscv: do not reimplement generic io functions [U-Boot,v2,12/29] riscv: complete the list of exception codes [U-Boot,v2,13/29] riscv: treat undefined exception codes as reserved [U-Boot,v2,14/29] riscv: hang on unhandled exceptions [U-Boot,v2,15/29] riscv: implement the invalidate_icache_* functions [U-Boot,v2,16/29] riscv: invalidate the instruction cache before jumping to Linux [U-Boot,v2,17/29] riscv: fix inconsistent use of spaces and tabs in start.S [U-Boot,v2,18/29] riscv: align mtvec on a 4-byte boundary [U-Boot,v2,19/29] Drop CONFIG_INIT_CRITICAL [U-Boot,v2,20/29] riscv: remove unused labels in start.S [U-Boot,v2,21/29] riscv: do not blindly modify the mstatus CSR [U-Boot,v2,22/29] riscv: save hart ID and device tree passed by prior boot stage [U-Boot,v2,23/29] riscv: qemu: use device tree passed by prior boot stage [U-Boot,v2,24/29] riscv: store device tree passed by prior boot stage in environment [U-Boot,v2,25/29] riscv: qemu: support booting Linux [U-Boot,v2,26/29] riscv: align bootm implementation with that of other architectures [U-Boot,v2,27/29] dm: core: add missing prototype for ofnode_read_u64 [U-Boot,v2,28/29] riscv: qemu: detect and boot the kernel passed by QEMU [U-Boot,v2,29/29] riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL

Commit Message

Lukas Auer Oct. 30, 2018, 12:55 p.m. UTC

Enable the -fdata-sections compiler option for RISC-V. Buildman reports
the binary size decrease from this as 8365.3 bytes.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
---

Changes in v2: None

 arch/riscv/config.mk | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

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Patch

diff --git a/arch/riscv/config.mk b/arch/riscv/config.mk
index 9088b9ef2c..b9487097f6 100644
--- a/arch/riscv/config.mk
+++ b/arch/riscv/config.mk
@@ -27,7 +27,8 @@  CONFIG_STANDALONE_LOAD_ADDR = 0x00000000 \
 			      -T $(srctree)/examples/standalone/riscv.lds
 
 PLATFORM_CPPFLAGS	+= -ffixed-gp -fpic
-PLATFORM_RELFLAGS	+= -fno-common -gdwarf-2 -ffunction-sections
+PLATFORM_RELFLAGS	+= -fno-common -gdwarf-2 -ffunction-sections \
+			   -fdata-sections
 LDFLAGS_u-boot		+= --gc-sections -static -pie
 
 EFI_CRT0		:= crt0_riscv_efi.o