diff mbox series

[U-Boot,v2,05/29] riscv: add Kconfig entries for the C and A ISA extensions

Message ID 20181030125553.5230-6-lukas.auer@aisec.fraunhofer.de
State Superseded
Delegated to: Andes
Headers show
Series General fixes / cleanup for RISC-V and improvements to qemu-riscv | expand

Commit Message

Lukas Auer Oct. 30, 2018, 12:55 p.m. UTC
Add Kconfig entries for the C (compressed instructions) and A (atomic
instructions) ISA extensions. Only the C ISA extension is selectable.
This matches the configuration in Linux.

The Kconfig entries are not used yet. A follow-up patch will select the
appropriate compiler flags based on the Kconfig configuration.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---

Changes in v2:
- Replace the description of RISCV_ISA_C with that of the Linux kernel,
as suggested by Bin Meng

 arch/riscv/Kconfig | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

Bin Meng Oct. 31, 2018, 2:13 a.m. UTC | #1
On Tue, Oct 30, 2018 at 8:57 PM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Add Kconfig entries for the C (compressed instructions) and A (atomic
> instructions) ISA extensions. Only the C ISA extension is selectable.
> This matches the configuration in Linux.
>
> The Kconfig entries are not used yet. A follow-up patch will select the
> appropriate compiler flags based on the Kconfig configuration.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
> Changes in v2:
> - Replace the description of RISCV_ISA_C with that of the Linux kernel,
> as suggested by Bin Meng
>
>  arch/riscv/Kconfig | 11 +++++++++++
>  1 file changed, 11 insertions(+)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox series

Patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index b81e0d990a..0de77a75d7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -38,6 +38,17 @@  config ARCH_RV64I
 
 endchoice
 
+config RISCV_ISA_C
+	bool "Emit compressed instructions"
+	default y
+	help
+	  Adds "C" to the ISA subsets that the toolchain is allowed to emit
+	  when building U-Boot, which results in compressed instructions in the
+	  U-Boot binary.
+
+config RISCV_ISA_A
+	def_bool y
+
 config 32BIT
 	bool